With the ever-increasing demand for AI and data-intensive applications, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$3\mathrm{D}$</tex> NAND Flash memories [1]–[6] need to achieve both high-density and high-speed IOS. Higher density can be attained by removing dummy holes in the cell array and increasing the number of stacked WLs. However, removal of dummy holes renders the GSL-cut process inapplicable [3]; thus, increasing power consumption due to the capacitance of unselected strings. Moreover, as the number of WLs increases, the amount of pass-voltage disturbance, which is directly related to the number of unselected WL, thereby deteriorating cell reliability. In addition, increased WL capacitance result in degradation of the program <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$({\mathrm{t}}_{\text{PROG}})$</tex> and read <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$({\mathrm{t}}_{\mathrm{R}})$</tex> time. Achieving high-speed <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{IOS}$</tex> also poses signal-integrity (SI) challenges: stringent eye-width (EW) and eye-height (EH) requirements; while also maintaining high 10 bandwidth and low-power consumption.