A jitter-filtering retimer is presented with a wide-bandwidth injection-locked oscillator (ILO) based input clock-and-data recovery (CDR) unit cascaded with a jitter filter phase-locked loop (PLL) that generates low-jitter clocks for the output transmitter that serializes and retimes the recovered data. The input ILO-based CDR employs a quarter-rate architecture for efficient wide-range operation and utilizes a digital loop filter with pattern filtering for robust input delay line and ILO frequency control. Fabricated in 28 nm CMOS, the proposed retimer operates from <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$12-20\text{Gb}/\mathrm{s}$</tex>, achieves the widest-reported <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$20\text{Gb}/\mathrm{s}$</tex> jitter tolerance (JTOL) of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1{\text{UI}}_{\text{PP}}$</tex> at a 173 MHz sinusoidal jitter (SJ) frequency and an estimated JTOL bandwidth in excess of 500 MHz, and consumes 58.66 mW.