Advancements in semiconductor technology have significantly improved the performance of DRAM and NAND flash, establishing them as high-speed main memory and high-capacity storage, respectively. However, the persistent performance gap between these two memory types remains a critical bottleneck in modern computing systems. To address this challenge, we propose a hybrid memory architecture, termed NAD, which tightly integrates DRAM and NAND flash to enable direct and parallel data transfer. By eliminating intermediate components such as I/O buffers and data buses typically used for inter-memory communication, the proposed NAD architecture significantly reduces data transfer latency. To validate its functionality, NAD memory was fabricated using a TSMC 180 nm CMOS logic process. Experimental results confirm reliable data transfer between DRAM and NAND flash, demonstrating the feasibility of NAD as a promising solution for overcoming memory bottlenecks in next-generation computing systems.