The continuous increase in functional density and operating frequency in modern electronic systems has intensified the design challenges associated with multilayer printed circuit boards (PCBs). Beyond ensuring basic connectivity, high-speed and high-density layouts must simultaneously satisfy signal integrity (SI), power integrity (PI), and electromagnetic compatibility (EMC) constraints. However, conventional maze-search-based autorouting algorithms, such as Lee’s algorithm and the A search method, primarily focus on minimizing routing length and computational effort, and thus fail to address multiobjective requirements including via minimization and conflict-free routing in three-dimensional (3D) design environments. In this study, an enhanced multilayer PCB autorouting algorithm is proposed. The proposed method extends the conventional A algorithm by adopting an eight-direction Chebyshev distance heuristic, a composite cost function that incorporates routing length and via penalties, and a dynamic re-routing mechanism for conflict resolution. The algorithm was evaluated using a representative two-layer dc–dc converter PCB layout. The proposed approach achieved 100% routing completion while reducing the average routing length by 21.55%, the number of vias by 50.00%, and the search time by 55.71% compared with the conventional A router. The results verify the effectiveness of the proposed algorithm for dense, constraint-driven PCB layouts and demonstrate its potential extension to SI- and EMC-aware autorouting in high-performance electronic systems.