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·2025
Laminated Ferroelectric Stack for Enhanced ISPP Slope and Endurance in FE-NAND
H. J. Lee, M. H. Sohn, Sijung Yoo, Yunseong Lee, Ki‐Hong Kim, Seung-Geol Nam, Yoonsang Park, Sanghyun Jo, Donghoon Kim, Jinseong Heo, Wanki Kim, Daewon Ha, Asif Islam Khan, Shimeng Yu, Duk‐Hyun Choe, Suman Datta
IF 4.5IEEE Electron Device Letters
초록

We present a ferroelectric NAND (FENAND) design that steepens the incremental step pulse programming (ISPP) slope and enhances reliability via a laminated FE stack. The laminate incorporates a 3 Å Al<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>O<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> interlayer at the mid-plane of a 15 nm HfZrO2 film. This structural modification reshapes the polarization-voltage loop, yielding a 25 % increase in coercive voltage (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V<sub>C</sub></i>) and a 19 % reduction in remnant polarization (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P<sub>r</sub></i>). Consequently, the ISPP slope improved by 16 %. The improvement stems from two effects: (1) Before switching, higher <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V<sub>C</sub></i> delays FE reversal, allowing more program voltage (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V<sub>PGM</sub></i>) to drop across the gate insulator (G.IL), strengthening the field and boosting gate-side injection. (2) After switching, reduced <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P<sub>r</sub></i> lowers the compensation charge at the channel interface, suppressing channel-side injection. Lowering charge injection through channel insulator (Ch.IL) during write, without sacrificing memory window (MW), mitigates dielectric stress, achieving 10-year retention and endurance up to 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> cycles. This FE stack design provides practical guidelines for scaling <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V<sub>PGM</sub></i> and spacer dimensions in high-density 3D FENAND.

키워드
Insulator (electricity)DielectricCoercivityStack (abstract data type)FerroelectricityVoltageCapacitorScalingPolarization (electrochemistry)Logic gate
타입
article
IF / 인용수
4.5 / 0
게재 연도
2025