This brief proposed an imbalanced inductor-current buck (IIB) converter. The proposed IIB converter has two inductor current paths. The IIB converter provides majority of the load current through a current path composed of low voltage transistors and minority of the load current through the current path composed of high voltage transistors, which becomes further as voltage conversion ratio decreases. Therefore, the IIB converter reduces conduction loss as the voltage conversion ratio decreases, which is considerably important in low voltage applications. In addition, since this converter uses a flying capacitor network behind the inductor, it is invulnerable to the input voltage variation. The proposed converter has peak efficiencies of 90.7% at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm{V}}_{\mathrm{IN}}=12$ </tex-math></inline-formula> V, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm{V}}_{\mathrm{O}}=0.6$ </tex-math></inline-formula> V, and 85.6% at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm{V}}_{\mathrm{IN}}=12$ </tex-math></inline-formula> V, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm{V}}_{\mathrm{O}}=0.3$ </tex-math></inline-formula> V. The chip was fabricated in 130-nm BCD process with an area of 6.177 mm2.