This letter proposes an n-type output capacitorless low-dropout regulator (LDO) with high power supply rejection (PSR) and fast transient response. To enhance both the performances, a multiple-feedback loop structure is proposed. The LDO obtained a PSR of –40 dB (–25 dB) at 1 MHz with load currents of 100 mA (600 mA). The LDO achieved an undershoot of 116 mV when the load changes from 1 to 600 mA, while consuming a quiescent current of 27.5 μA. The chip was fabricated in the 180-nm CMOS process with an area of 0.063 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.