Charge domain SRAM-based Process-In-Memory (PIM) has been tremendously researched for recent years to improve throughput and energy efficiency in data intensive neural network applications. However, there are two main issues that need to be resolved in charge domain SRAM-based PIM architectures, 1) minimizing area overhead while supporting multi bit Multiply-and-Accumulate (MAC) operation, 2) addressing the MAC operation gain error and offset error due to PVT-varied input Digital-to-Analog data Converters (DACs) and in-array coupling noises, respectively.