김은성 교수 연구실
2024
A 3.5 to 4.7-GHz Fractional-N ADPLL With a Low-Power Time-Interleaved GRO-TDC of 6.2-ps Resolution in 65-nm CMOS Process
Cho Kyoung-Ub, Gil Joonho, Park Chulhyun, Cho Kyu-Jin, Shin Jae-Woo, Kim Eun-Seong, Eo Yun-Seong, Harjani Ramesh, Kim Nam-Young, Oh Taehyoun
타입
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IF / 인용수
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원문
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게재 연도
2024