The growing demand for heterogeneous computing in AI workloads has heightened the need for efficient CPU–accelerator communication. For this purpose, PCI Express (PCIe) has emerged as the dominant interconnect in recent systems. However, current architectural simulators provide limited support for accurate performance evaluation of PCIe devices. In this paper, we present a guideline to extend the gem5 simulator for arbitrary PCIe device integration. While gem5 is widely used for CPU simulation and architectural exploration, it only supports a limited set of PCI devices and lacks a standardized framework. By analyzing the mechanisms of gem5, particularly its support for AMD GPUs, we identify key components involved in communication: MMIO, DMA, and interrupts. Based on these insights, we propose a methodology for integrating arbitrary PCIe device simulators into gem5, enabling development of heterogeneous systems.