This paper presents an energy-efficient ADC-based PAM4 receiver fabricated in a 28 nm CMOS process. The proposed design features a four-way time-interleaved charge-based subranging ADC that integrates three key techniques: 1) a wide input-tolerant charge-based comparator that extends the limited input range and improves operational robustness of conventional low-power charge-based comparators, 2) a conditional-branching-based partial activation scheme that improves the area and capacitive efficiency of the subranging architecture, and 3) a time-based calibration technique that addresses potential performance degradation in the conditional branching scheme. These design techniques enable robust and power-efficient ADC operation optimized for high-speed applications while minimizing the interleaving factor. The prototype ADC achieves an SNDR of 29.1 dB (ENOB = 4.54 bits) at 4 GHz input and 8 GS/s. Operating at 20 Gb/s under a 33.1 dB insertion loss channel, the proposed receiver effectively compensates for ISI, achieving a pre-FEC BER of 1.8E-8 with a competitive energy efficiency of 3.09 pJ/b. These results demonstrate that the proposed low-interleaving architecture provides a scalable and power-efficient solution for high-speed wireline communication.