The general approach to suppress leakage in static random access memory (SRAM) is to use a low voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\text{L}}$</tex-math> </inline-formula>), generated by a low-dropout regulator (LDO), as the cell supply voltage (CVDD) of SRAM array in the standby mode. However, the effectiveness of lowering CVDD is constrained by the area and power overhead introduced by the LDO, as well as the additional latency and power consumption incurred during mode switching. This work presents a fully voltage-stacked (FVS) SRAM that reduces leakage power with internally generated intermediate voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\text{MID}}$</tex-math> </inline-formula>) by stacking SRAM arrays. The FVS SRAM consists of a foundry high-density (HD) cell and a pMOS pass-gate (PG) cell having the same metal pattern and size as the HD cell, ensuring compatibility across various process nodes. In addition, the FVS SRAM reduces minimum operating voltage and access energy by the intermediate cell voltage (ICV) assist technique and charge-sharing-based precharge, respectively. The silicon measurement results from a 14-nm FinFET test chip demonstrate that the FVS SRAM achieves a leakage power of 5.34 pW/bit and an access energy of 24.6 fJ/bit at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\text{MIN}}=0.5$</tex-math> </inline-formula>V. Compared to conventional non-stacked SRAM, the FVS SRAM exhibits 29%–59% and 10%–21% reduction in leakage power and access energy across VDD <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$=0.6$</tex-math> </inline-formula>–0.8 V.