This article presents DPe-CIM, a 4T-1C dual-port embedded dynamic random access memory (eDRAM)-based compute-in-memory (CIM) macro with adaptive refresh and data conversion reduction. DPe-CIM proposes four key features that improve area and energy efficiency: 1) dual-port eDRAM cell (DPC) separates the multiply-and-accumulate (MAC) and refresh ports, enabling simultaneous MAC and refresh (SMR) operation to eliminate wasted cycles for refresh; 2) adaptive refresh tracking (ART) eliminates unnecessary refresh power consumption; 3) bitline (BL) embedded DAC (BLe-DAC) enhances area and energy efficiency with BL capacitance reuse; 4) output-boosting ADC (OB-ADC) with charge analog adder (CAA) reduces ADC precision and number of ADC per row without accuracy loss to save area and energy in ADC, thereby overcoming CIM efficiency wall. The DPe-CIM is fabricated in 28-nm CMOS technology and occupies 0.0496 mm<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}^2$</tex-math> </inline-formula> with 72-kb cell capacity. Its measured memory density is 1.42 Mb/mm<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}^2$</tex-math> </inline-formula>, reaches a peak MAC density of 13.85 TOPS/mm<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}^2$</tex-math> </inline-formula>, and a peak energy efficiency of 505.83 TOPS/W performing 4-b−4-b operations. DPe-CIM achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.56\times$</tex-math> </inline-formula> higher computing efficiency figure of merit (FoM) than the previous CIM architectures.