We present a fully analytical model and physical investigation on the source resistance (<i>R_S</i>) in In<i>_x</i>Ga<i>_1-x</i>As quantum-well high-electron mobility transistors based on a three-layer TLM system. The <i>R_S</i> model in this work was derived by solving the coupled quadratic differential equations for each current component with appropriate boundary conditions, requiring only six physical and geometrical parameters, including ohmic contact resistivity (<i>ρ_c</i>), barrier tunneling resistivity (<i>ρ_barrier</i>), sheet resistances of the cap and channel regions (<i>R_{sh_cap}</i> and <i>R_{sh_ch}</i>), side-recessed length (<i>L_side</i>) and gate-to-source length (<i>L_gs</i>). To extract each model parameter, we fabricated two different TLM structures, such as <i>cap-TLM</i> and <i>recessed-TLM</i>. The developed <i>R_S</i> model in this work was in excellent agreement with the <i>R_S</i> values measured from the two TLM devices and previously reported short-<i>L_g</i> HEMT devices. The findings in this work revealed that barrier tunneling resistivity already played a critical role in reducing the value of <i>R_S</i> in state-of-the-art HEMTs. Unless the barrier tunneling resistivity is reduced considerably, innovative engineering on the ohmic contact characteristics and gate-to-source spacing would only marginally improve the device performance.