This article addresses issues with designing a blind oversampling clock and data recovery unit (CDR) that meets jitter tolerance specifications. Asymptotic limits on jitter tolerance are derived assuming ideal phase detection based on a priori statistics of the received signal, proving that the coarse timing resolution of blind oversampling CDR relies on a phase detection algorithm that makes good estimates of the signal's statistics with a finite number of discrete samples and at reasonable hardware costs. The statistical simulation methodology outlined here enables quick verification of the bit error rate and comparisons between the jitter tolerances of various blind oversampling CDR architectures.