High bandwidth memory (HBM) has enabled a breakthrough in bandwidth-bound applications, including large-scale artificial intelligence models. HBM is typically connected to other SoCs through a silicon interposer. However, the increasing density of the parallel interconnect wires incurs significant amount of crosstalk, hindering bandwidth improvement in the next-generation HBMs. While Crosstalk Avoidance Code (CAC) has emerged as a solution to mitigate crosstalk, prior CAC schemes suffer from low bit efficiency and significant hardware overhead. This paper proposes an efficient CAC scheme, WITCH. It employs a new coding system, weighted coding, which gives a different emphasis to each channel according to its relative position in the channel array. This enables crosstalk reduction with higher bit efficiency than prior CACs treating all channels in the array equally. The extended version of WITCH, WITCH-AS, is also proposed with additional shielding for further crosstalk reduction. Our coding system shows high bit efficiency of 91.2--91.7% and 84.3--84.6% for WITCH and WITCH-AS, which is up to 20.8% higher than the state-of-the-art schemes while preserving the same crosstalk level reduction. We have shown through simulations using an industry-proven channel model that WITCH and WITCH-AS improve the eye heights by 10.1--49.4% and 17.1--51.1% respectively. In addition, this paper presents an efficient hardware implementation of our coding schemes which shows 28.2% lower critical path delay and 31.0% smaller area than conventional implementation, proving itself a practical solution for HBMs.