This paper presents a synthesizable quarter-rate CDR based on a fractional-N ADPLL, designed in a 28-nm CMOS process for 32 Gb/s operation. The architecture integrates a quadrature rotational frequency detector (Q-RFD), a bang-bang phase detector (PD), and an N-filter to enable robust frequency acquisition and fine phase alignment. Post-layout simulations confirm locking from a 30,000 ppm frequency error within 11 μs and residual frequency error below 50 ppm. The design achieves 1.3 ps RMS jitter and occupies less than 0.016 mm², offering strong PVT robustness and suitability for high-speed serial links.