Split capacitor digital-to-analog converters (split-CDACs) are a promising method to reduce area but face challenges with parasitic sensitivity in high-resolution settings for successive approximation register analog-to-digital converters (SAR ADCs) design. This article introduces a split-CDAC design for improving area efficiency for higher bit resolution by reducing parasitic sensitivity and mismatch. A fundamental reason for the increased parasitic sensitivity stems from the fractional sizing of the bridge capacitor and a small redundant capacitor at the split node. The proposed split-CDAC uses a unit capacitor-based bridge capacitor and a proportionally scaled large redundant unit capacitor, which minimizes these effects to a large extent while achieving linearity. It achieves six times better parasitic sensitivity than a conventional split-CDAC by using six-unit capacitors as a bridge capacitor and 12 times better area efficiency than the conventional binary-weighted CDAC. The proposed fully common-centroided and shielded unit capacitor array, implemented in a 65 nm CMOS process, effectively reduces parasitic and mismatch sensitivity using a simple layout structure. The implementation achieves an INL of less than 1.2 LSB, measured across 21 chips, without mismatch calibration and opens new possibilities for high-precision applications across diverse domains.