We demonstrate a high-performance and low-noise single-chip sub-terahertz (THz) imager array by integrating ground (gnd)-out trantenna (transistor-antenna) with a reset switch, analog buffer, multiplexer, and preamplifier using 65-nm CMOS technology. The channel charge asymmetry of sub-THz pixel device is enhanced with ac-gnd and ac-open load impedance design for gnd-out and gnd-in trantenna, respectively. The reset modulation switch suppresses output overshoot. Thus, the detector delay time of gnd-out trantenna, with a considerably smaller output junction capacitance than gnd-in trantenna, is reduced to sub-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$ </tex-math></inline-formula>s regime. In 0.1-THz direct illumination setup, the gnd-out trantenna with analog buffer circuitry experimentally achieves high-speed sub-THz imager operation up to 600 kHz with a commercial-level delay time <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$=0.98\mu$ </tex-math></inline-formula>s (15 times faster than gnd-in case). Owing to low-impedance analog buffer design for gnd-out trantenna with high-speed reset switch modulation (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 300$ </tex-math></inline-formula> kHz), a high responsivity (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$R_V=620$ </tex-math></inline-formula> kV/W) and ultralow noise-equivalent power (NEP <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$=8.44$ </tex-math></inline-formula> pW/Hz0.5) are obtained for the peripheral circuitry-integrated sub-THz imager.