Evaluating the clock quality of a device's phase-locked loop (PLL) using automatic test equipment (ATE) at an affordable cost is challenging due to the large number of channels and long test times required. This study proposes a new low-cost method for testing the clock jitter of the device using PLL, delay, gate, etc. in the FPGA. Using this circuit, the total jitter analysis function of an expensive, heavy, and slow oscilloscope can be performed simultaneously with tens of CH of clocks within 1us time on a smart phone size board with only tens of dollars of FPGA.