This paper presents a switched-capacitor-driven on-chip interface (S-CDI) that enhances signal integrity and maintains a stable channel DC bias at Vdd/2. It employs alternating pre-charging and charge-sharing using dual series capacitors (Cup/Cdn). This approach enables the use of smaller capacitance while maintaining comparable signal swing to that of prior cap-driven interfaces, leading to higher bandwidth and improved eye-opening margin. Fabricated in a 28 nm CMOS process, the S-CDI achieves 15.2 Gb/s and 13.8 Gb/s over a 6-mm on-chip interconnect for PRBS7 and PRBS31 patterns, respectively. It demonstrates the fastest normalized speed among prior arts: <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$316\text{Gb}/\mathrm{s}\cdot {\text{mm}}^2/{\mu }^2$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$286.9\text{Gb}/\mathrm{s}\cdot {\text{mm}}^2/{\mu }^2$</tex> for PRBS7 and PRBS31. At 15.2 Gb/s with PRBS7, it achieves 468 fJ/b energy efficiency and a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">${\text{FoM}}_{\text{dB}}$</tex> of 23.5 fJ/b/dB.