Spatial charge trap engineering using amorphous boron nitride (BN) energy barrier for 3D V-NAND flash memory device is presented. A 1 nm thick BN layer is inserted within a silicon nitride (SiN) charge trap layer (CTL) using an In-situ ALD process. The CTL with the BN barrier located at an optimized position showed clear advantages in memory window and charge retention. The advantage of using the BN barrier becomes even more apparent when the CTL is scaled down to 4 nm, having more than 20% larger memory window, 44% improvement in hole retention, and more than 10 times faster erase speed compared to the same thickness of pure SiN CTL, which helps to advance XY-scaling in 3D V-NAND flash devices.