Most modern operating systems have adopted the one-to-one thread model to support fast execution of threads in both multi-core and single-core systems. This thread model, which maps the kernel-space and user-space threads in a one-to-one manner, supports quick thread creation and termination in high-performance server environments. However, the performance of time-critical threads is degraded when multiple threads are being run in low-end CE devices with limited system resources. When a CE device runs many threads to support diverse application functionalities, low-level hardware specifications often lead to significant resource contention among the threads trying to obtain system resources. As a result, the operating system encounters challenges, such as excessive thread context switching overhead, execution delay of time-critical threads, and a lack of virtual memory for thread stacks. This article proposes a state-of-the-art Thread Evolution Kit (TEK) that consists of three primary components: a CPU Mediator, Stack Tuner, and Enhanced Thread Identifier. From the experiment, we can see that the proposed scheme significantly improves user responsiveness (7× faster) under high CPU contention compared to the traditional thread model. Also, TEK solves the segmentation fault problem that frequently occurs when a CE application increases the number of threads during its execution.

Multi-user surface computing systems are promising for the next generation consumer electronics devices due to their convenience and excellent usability. However, conventional resource scheduling schemes can cause severe performance issues in surface computing systems, especially when they are adopted in multi-user environments, because they do not consider the characteristics of multi-user surface computing systems. In this paper, we propose an efficient user-based resource scheduling scheme for multi-user surface computing systems, called URS. URS provides three different features to effectively support multi-user surface computing systems. First, URS distributes system resources to users, according to their real-world priorities, rather than processes or tasks. Second, URS provides performance isolation among multiple users to prevent resource monopoly by a single user. Finally, URS prioritizes a foreground application of each user via retaining pages used by the application in the page cache, in order to enhance multi-user experience. Our experimental results confirm that URS effectively allocates system resources to multiple users by providing the aforementioned three features.

A crash-consistency mechanism of database application (hereinafter DBMS for short) imposes an enormous burden on the journaling process of the file system (e.g., JBD2) in that it employs regular files on the file system to persistently preserve the application's journal data with synchronous system calls. Unfortunately, much of the previous research is impractical in real-world scenarios because they require changing a lot of source lines of code in multiple software layers of the software stack or using special hardware (e.g., the transactional flash storage or NVM technologies). In this paper, we propose a new journal mode of DBMS, called S-WAL, which compresses the raw data journaled by the database to alleviate both the redundant journaling operations and harmful write amplification. We believe that S-WAL is a practical way to support application-level crash consistency on the existing mobile devices because only a few lines of DBMS code need to be changed, without the need to employ special hardware. We demonstrate the effectiveness of S-WAL by running four popular mobile applications on the latest smartphone. Our evaluation results show that S-WAL considerably outperforms existing journal modes of DBMS in all cases. In the best case, S-WAL reduces the elapsed time by up to 7.5× more than the PERSIST mode and by up to 51% more than the traditional WAL mode.

In recent years, almost all consumer devices adopt NAND flash storage as their main storage, and the performance and capacity requirements for the storage components are increasing. To meet the requirements, many researchers and manufacturers have focused on combined SLC-TLC storage, which consists of high-speed single-level cell (SLC) and high-density triple-level cell (TLC) memory. In this paper, we re-design the internal structure of the combined SLC-TLC storage to improve its performance and lifetime. We also add new behavior by employing the I/O characteristics of the file system journaling to efficiently manage the SLC region inside the storage. We implemented our scheme on a real storage platform and compared its performance with those of the conventional techniques. The results of our evaluation show that our scheme improves the storage performance by up to 65% relative to the conventional techniques.

Today, flash storage devices have become a standard storage in consumer electronics devices, such as smartphones, smart tablets, and smart TVs, due to their attractive features. Since flash storage helps to cut down on system response for customers, consumer devices based on the flash storage are gradually increasing. Unfortunately, the flash storage of consumer electronics devices suffers from random write requests because applications running on the consumer device simultaneously issue a lot of write operations to store their persistent data. This paper proposes a novel write buffer algorithm, called Clock with DRAM and NVM hybrid write buffer (CLOCK-DNV), that reshapes random write requests into sequential ones. In order to maximize the number of consecutive write requests, CLOCK-DNV takes the benefits of NVM media with the dirty page padding mechanism. For extensive evaluation, the proposed algorithm is implemented on a flash storage simulator, which is widely used for performance analysis, and is compared with two write buffer algorithms, FAB and CBM. The evaluation results clearly show that CLOCK-DNV maintains higher hit ratios than other write buffer algorithms. Moreover, CLOCK-DNV efficiently reduces the number of write requests issued to the underlying flash memory by up to 56% compared with the state-of-the-art algorithm, CBM, while extending the endurance of flash storage by up to 56%.

Advances in memory technologies ( e . g ., HBM, DRAM, NVM) and interconnects ( e . g ., CXL) have significantly enhanced the flexibility of utilizing memory resources in modern computer systems. As this trend continues, memory resources are poised to become fully composable in the near future. This increasing flexibility also accelerates the demand for effective tiered memory systems capable of performing well across diverse scenarios and workloads. However, the effectiveness of existing tiered memory systems heavily depends on system configuration (e.g., the ratio of fast tier to capacity tier), memory access patterns, and page sizes (base vs. huge). Their reliance on simple heuristics and static thresholds for detecting page hotness, and limited consideration of page sizes, results in suboptimal (often pathological) page placement decisions. To build a robust and effective system, tiered memory management must holistically account for overall memory access patterns in conjunction with the tiering environment. We present Memtis , a tiered memory system that adopts informed decision-making for page placement and page size determination. Memtis leverages access distribution of allocated pages to optimally approximate the hot data set to the fast tier capacity. Moreover, Memtis dynamically determines the page size that allows applications to use huge pages while avoiding their drawbacks by detecting inefficient use of fast tier memory and splintering them if necessary. To further enhance its practicality across diverse scenarios, Memtis effectively supports the dynamic allocation of fast tier memory if there is a specific performance requirement, such as a target hit ratio. Our evaluation shows that Memtis outperforms existing tiered memory systems under various workloads and tiering configurations by up to 169.0%, showing its robustness.

This paper presents a hierarchical dispatcher architecture designed to efficiently schedule the execution of multiple deep neural networks (DNNs) on edge devices with heterogeneous processing units (PUs). The proposed architecture is applicable to systems where PUs are either integrated on a single edge device or distributed across multiple devices. We separate the dispatcher and scheduling policy. The dispatcher in our framework acts as a mechanism for allocating, executing, and managing subgraphs of DNNs across various PUs, and the scheduling policy generates optimized scheduling sequences. We formalize a hierarchical structure consisting of high-level and low-level dispatchers, which together provide scalable and flexible scheduling support for diverse DNN workloads. The high-level dispatcher oversees the partitioning and distribution of subgraphs, while the low-level dispatcher handles the execution and coordination of subgraphs on allocated PUs. This separation of responsibilities allows the architecture to efficiently manage workloads in both homogeneous and heterogeneous environments. Through case studies on edge devices, we demonstrate the practicality of the proposed architecture. By integrating appropriate scheduling policies, our approach achieves an average performance improvement of 51.6%, providing a scalable and adaptable solution for deploying deep learning models on heterogeneous edge systems.

In multi-container environments, applications oftentimes experience unexpected performance fluctuations due to undesirable interference among applications. Synchronization such as locks has been targeted as one of the reasons but still remains an uncontrolled resource while a large set of locks are still shared across applications. In this paper, we demonstrate that this lack of lock scheduling incurs significant real-world problems including performance unfairness and interference among applications. To address this problem, we propose a new synchronization design with an embedded scheduling capability, called CFL (Completely Fair Locking). CFL fairly distributes a fair amount of lock occupation time to applications considering their priorities and cgroup information. For scalability, CFL also considers the NUMA topology in the case of NUMA machines. Experimental results demonstrate that CFL significantly improves performance fairness while achieving comparable or sometimes even superior performance to state-of-the-art locks.

In recent years, ZNS has attracted mobile manufacturers with its fascinating features and is expected to be merged into the mobile I/O subsystem. In the meantime, F2FS is one of the feasible options to support ZNS in mobile devices since F2FS adopts append-only write policy. However, F2FS significantly suffers from filesystem-level garbage collection (GC) and it increases the tail latency of foreground applications. To overcome this problem, we propose a new F2FS GC scheme, which preempts the ongoing GC when it is beneficial, in order to prevent the foreground applications from waiting for a long time. Our evaluation demonstrates that our scheme reduces the tail latency of foreground applications by up to 87%, compared with the conventional F2FS GC scheme.