발행물
컨퍼런스
IEEE ASSCC
2021
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An Input-Buffer Embedding Dual-Residue Pipelined-SAR ADC with Nonbinary Capacitive Interpolation
IEEE Symposium on VLSI Circuits
2020
An 8b 1GS/s 2.55mW SAR-Flash ADC with Complementary Dynamic Amplifiers
2019
A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability
A 40nm CMOS 12b 200MS/s Single-Amplifier Dual-Residue Pipelined-SAR ADC
A 6b 28GS/s 4-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration