In this paper, an optimal design of a high-efficiency DC-DC boost converter is proposed for RF energy harvesting Internet of Things (IoT) sensors. Since the output DC voltage of the RF-DC rectifier for RF energy harvesting varies considerably depending on the RF input power, the DC-DC boost converter following the RF-DC rectifier is required to achieve high power conversion efficiency (PCE) in a wide input voltage range. Therefore, based on the loss analysis and modeling of an inductor-based DC-DC boost converter, an optimal design method of design parameters, including inductance and peak inductor current, is proposed to obtain the maximum PCE by minimizing the total loss according to different input voltages in a wide input voltage range. A high-efficiency DC-DC boost converter for RF energy harvesting applications is designed using a 65 nm CMOS process. The modeled total losses agree well with the circuit simulation results and the proposed loss modeling results accurately predict the optimal design parameters to obtain the maximum PCE. Based on the proposed loss modeling, the optimally designed DC-DC boost converter achieves a power conversion efficiency of 96.5% at a low input voltage of 0.1 V and a peak efficiency of 98.4% at an input voltage of 0.4 V.

In this paper, a fully integrated capacitive DC-DC boost converter for ultra-low-power internet of things (IoT) applications operating with RF energy harvesting is proposed. A DC-DC boost converter is needed to boost the low output voltage of the RF energy harvester to provide a high voltage to the load. However, a boost converter operating at a low voltage supplied by ambient RF energy harvesting has a problem in that power conversion efficiency is significantly lowered. The proposed on-chip capacitive DC-DC boost converter simultaneously applies gate bias boosting and dynamic body biasing techniques using only the internal boosted voltage without an additional circuit that increases power loss to boost the voltage, achieving high efficiency at an input voltage as low as 0.1 V. The designed capacitive boost converter achieves a peak power conversion efficiency (PCE) of 33.8% at a very low input voltage of 0.1 V, a 14% improvement over the peak PCE of the conventional cross-coupled charge pump. A maximum peak PCE of 80.1% is achieved at an input voltage of 200 mV and a load current of 3 μA. The proposed capacitive boost converter is implemented with a total flying capacitance of 60 pF, suitable for on-chip integration.

The Metal Oxide Surge Arrester (MOSA) was developed for the purpose of overvoltage protection in electrical systems, protecting electrical equipment from overvoltage caused by lightning strikes, switching operations, and fault conditions. In the interrupting process of the MVDC Circuit Breaker, the MOSA encounters large fault currents and must endure significant thermal and dielectric stresses due to long duration conduction. The MOSA is designed with a parallel stack of Metal Oxide Varistors (MOV) to enable it to withstand high thermal capacity and significant dielectric stress. However, the parallel stack of the MOSA leads to current imbalances, resulting in thermal stress across the stacks and consequently degrading the performance of the MVDC Circuit Breaker. In this paper, a 42kV 9kA Short Circuit Current Test-bed for evaluating the performance of MOSA in MVDC circuit breakers was simulated using PSCAD/EMTDC software. Under conditions of current imbalance in MOSA, the study compared transient interruption voltage, interruption time, and absorbed energy based on the number of columns. The study analyzed the impact of column numbers on the interrupting performance of MVDC circuit breakers during the interrupting process.

This paper presents a design of an advanced pulse-train time amplifier (A-PTTA) that utilizes an active off-state time control to minimize the skew error and conversion rate in the radiation environments. Three D-flip-flops are employed to provide an overlap code (O-code), determining whether overlap occurs between the first input pulse and subsequent pulses. The output of the time amplifier is determined by selecting one of the delay chains based on the O-code. The proposed A-PTTA was verified using an electronic design automation tool, demonstrating the maximum improvement of 70% in conversion time. The proposed circuit was fabricated using general-purpose $0.18\mu \mathrm{m}$ CMOS technology, and the test results will be discussed at the conference.

This paper presents a radiation-hardened-by-design (RHBD) preamplifier that utilizes a self-reset technique when the preamplifier becomes saturated. The proposed RHBD preamplifier comprises the charge-sensitive amplifier (CSA) part with the self-reset circuit and total ionizing dose (TID) effects compensation part. The CSA part consists of a comparator, a feedback switch, and a trigger circuit. The trigger circuit generates a pulse with sufficient duration to reset the feedback capacitor when the CSA becomes saturated. TID effects compensation part utilizes a binary current source to compensate TID effects in the CSA. The current source control unit detects the operating point of the OPAMP and generates appropriate signals to control the current source switches. The proposed circuit was fabricated using general-purpose 0.18 μm CMOS technology, and verified through an irradiation test up to 231 kGy (SiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>) at a rate of 10.46 kGy/h.

The detector capacitance compensation (DCC) technique which achieves double active quenching of single-photon avalanche diode (SPAD) is presented in this paper. A well-defined active quenching circuit has the advantages of a higher maximum photon-counting rate and lower afterpulsing probability. Quenching time and area are important criteria when implementing an active quenching circuit. The proposed novel active quenching circuit employing the DCC technique achieves 2.5 times better quenching time than the conventional one, with an area increase of just 23%. The schematic and simulation results are shown in this paper. Designed circuits are fabricated and simulated in 180 nm CMOS technology.

An ultralow-power ultrawideband (UWB) transmitter with an energy-efficient injection-locked radio frequency (RF) clock harvester that generates a carrier from an RF signal is proposed for RF energy-harvesting Internet-of-Things (IoT) sensor applications. The energy-efficient RF clock harvester based on the injection-locked ring oscillator (ILRO) is proposed to achieve optimal locking range and minimum input sensitivity to obtain an injection-locked 450 MHz clock in ultralow-power operation. A current-starved inverter-based delay stage is adopted that allows delay adjustment by bias voltage to minimize dynamic current consumption while maintaining a constant delay regardless of changes in process, supply voltage, and temperature (PVT). To minimize static current consumption, a UWB transmitter based on a digital-based UWB pulse generator and a pulse-driven switching drive amplifier is proposed. The proposed injection-locked RF clock harvester achieves the best RF input sensitivity of -34 dBm at a power consumption of 2.03 μW, enabling energy-efficient clock harvesting from low RF input power. In ultralow-power operation, a 23.8% locking range is achieved at the RF injection power of -15 dBm to cope with frequency changes due to PVT variations. The proposed UWB transmitter with RF clock harvester achieves the lowest energy consumption per pulse with an average power consumption of 97.03 μW and an energy consumption of 19.41 pJ/pulse, enabling operation with the energy available in RF energy-harvesting applications.

In this paper, a dual-band wide-input-range adaptive radio frequency-to-direct current (RF-DC) converter operating in the 0.9 GHz and 2.4 GHz bands is proposed for ambient RF energy harvesting. The proposed dual-band RF-DC converter adopts a dual-band impedance-matching network to harvest RF energy from multiple frequency bands. To solve the problem consisting in the great degradation of the power conversion efficiency (PCE) of a multi-band rectifier according to the RF input power range because the available RF input power range is different according to the frequency band, the proposed dual-band RF rectifier adopts an adaptive configuration that changes the operation mode so that the number of stages is optimized. Since the optimum peak PCE can be obtained according to the RF input power, the PCE can be increased over a wide RF input power range of multiple bands. When dual-band RF input powers of 0.9 GHz and 2.4 GHz were applied, a peak PCE of 67.1% at an input power of -12 dBm and a peak PCE of 62.9% at an input power of -19 dBm were achieved. The input sensitivity to obtain an output voltage of 1 V was -17 dBm, and the RF input power range with a PCE greater than 20% was 21 dB. The proposed design achieved the highest peak PCE and the widest RF input power range compared with previously reported CMOS multi-band rectifiers.

In this paper, an optimal design of a high-efficiency DC-DC boost converter is proposed for RF energy harvesting Internet of Things (IoT) sensors. Since the output DC voltage of the RF-DC rectifier for RF energy harvesting varies considerably depending on the RF input power, the DC-DC boost converter following the RF-DC rectifier is required to achieve high power conversion efficiency (PCE) in a wide input voltage range. Therefore, based on the loss analysis and modeling of an inductor-based DC-DC boost converter, an optimal design method of design parameters, including inductance and peak inductor current, is proposed to obtain the maximum PCE by minimizing the total loss according to different input voltages in a wide input voltage range. A high-efficiency DC-DC boost converter for RF energy harvesting applications is designed using a 65 nm CMOS process. The modeled total losses agree well with the circuit simulation results and the proposed loss modeling results accurately predict the optimal design parameters to obtain the maximum PCE. Based on the proposed loss modeling, the optimally designed DC-DC boost converter achieves a power conversion efficiency of 96.5% at a low input voltage of 0.1 V and a peak efficiency of 98.4% at an input voltage of 0.4 V.