발행물
컨퍼런스
SoC 학술대회
2018
,
TFET 기반 표준 셀 레이아웃 방법 및 배치 최적화
Conference on Design-Process-Technology Co-Optimization for Manufacturability XII
A Compact Multi-Bit Flip-Flop with Smaller Height Implementation and Metal-Less Intra-Cell Routing
SPIE Advanced Lithography
Timing optimization in SADP process through wire widening and double via insertion
A compact multi-bit flip-flop with smaller height implementation and metal-less clock routing
제25회 한국반도체학술대회
Automatic clock gating synthesis through detection of cyclic paths