SAR-Assisted Energy-Efficient Hybrid ADCs

MixedNet: A Network Design Strategies for Cost-effective Quantized Convolutional Neural Network

A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-ranging SAR ADC with On-Chip Background Skew Calibration

Compact Mixed-Signal Convolutional Neural Network Using a Single Modular Neuron

A 40-nm CMOS 12b 120-MS/s Nonbinary SAR-Assisted SAR ADC with Double Clock-Rate Coarse Decision

A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks

A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration

A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8x Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration

Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC

A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC