As the demand for high-speed memory interfaces continues to grow, the need for effective testing methodologies becomes increasingly critical. Traditional automatic test equipment (ATE) systems are limited in their capability to test advanced signaling methods such as pulse amplitude modulation-4 (PAM-4) due to their reliance on non-return-to-zero (NRZ) signaling. This article presents a PAM-4 transceiver designed to bridge the gap between the tester and the memory, boosting the PAM-4 testing data rate up to 48 Gb/s using existing NRZ-based ATE. The proposed work provides enhanced transition slope and ratio level mismatch (RLM) control through precise gate voltage adjustment, resulting in improved test accuracy. The prototype was fabricated in 40-nm CMOS technology and occupies an active area of 2.34 mm². The proposed work operates at 48 Gb/s/pin, demonstrating an energy efficiency of 1.85 pJ/bit in write mode and 2.97 pJ/bit in read mode for the PAM-4 test, respectively.

This article presents a design methodology for compact single-channel 1 GS/s 8-bit 3-stage capacitor-array-assisted charge-injection DAC-based SAR ADC. A detailed framework of an information rate density (IRD) is mainly investigated in this work. With the proposed framework, an 8-bit prototype ADC reaches the highest IRD thanks to the optimum choice of DAC construction. To improve the performance of the ADC, we propose various circuit techniques such as 1) DC dependence compensation of charge-injection cell (ci-cell), 2) up-then-down DAC switching sequence, and 3) metastability detection to prevent the sparkle code error. The prototype ADC was fabricated in a 28-nm CMOS process and occupies an ultra-compact active area of 0.000261 mm2, the smallest among the previously reported designs. At a 1.0 V supply voltage and 1 GS/s operation, the proposed ADC achieves an SNDR of 43.5 dB and dissipates 2.61 mW at the Nyquist rate, resulting in the state-of-the-art IRD of 470 TS/s $\cdot$ conv/mm2.

This letter presents a 4.5-to-14 GHz phase-locked loop (PLL)-based clock driver with wide-range 3-shaped LC-VCOs for GDDR6 DRAM test. We use two frequency modes to generate a write clock (WCK) from DC-to-14 GHz. In low-frequency mode under 4.5 GHz, the input from the automatic test equipment (ATE) is bypassed to WCK output. In high-frequency mode, PLL supports high-frequency WCK with good phase noise employing LC-VCOs. We propose 3 LC-VCOs to cover 48 frequency bands which support a frequency range from 4.5-to-14 GHz. Moreover, the current-mode driver with output common mode level control is proposed to provide programmability of the received clock input crossing point for the GDDR6 DRAM test. The prototype chip was fabricated in a 40 nm CMOS technology. The measured frequency tuning range is from 4.5-to-14 GHz with a tuning ratio of 102.7 %. The measured output common mode peak-to-peak difference is 200 mV. The measured integrated RMS jitter is 129 f_srms at 7 GHz, 180 fs_rms at 11 GHz, and 365 fs_rms at 14 GHz, respectively.

As the demand for high-speed memory interfaces continues to grow, the need for effective testing methodologies becomes increasingly critical. Traditional automatic test equipment (ATE) systems are limited in their capability to test advanced signaling methods such as pulse amplitude modulation-4 (PAM-4) due to their reliance on non-return-to-zero (NRZ) signaling. This article presents a PAM-4 transceiver designed to bridge the gap between the tester and the memory, boosting the PAM-4 testing data rate up to 48 Gb/s using existing NRZ-based ATE. The proposed work provides enhanced transition slope and ratio level mismatch (RLM) control through precise gate voltage adjustment, resulting in improved test accuracy. The prototype was fabricated in 40-nm CMOS technology and occupies an active area of 2.34 mm². The proposed work operates at 48 Gb/s/pin, demonstrating an energy efficiency of 1.85 pJ/bit in write mode and 2.97 pJ/bit in read mode for the PAM-4 test, respectively.

This article presents a design methodology for compact single-channel 1 GS/s 8-bit 3-stage capacitor-array-assisted charge-injection DAC-based SAR ADC. A detailed framework of an information rate density (IRD) is mainly investigated in this work. With the proposed framework, an 8-bit prototype ADC reaches the highest IRD thanks to the optimum choice of DAC construction. To improve the performance of the ADC, we propose various circuit techniques such as 1) DC dependence compensation of charge-injection cell (ci-cell), 2) up-then-down DAC switching sequence, and 3) metastability detection to prevent the sparkle code error. The prototype ADC was fabricated in a 28-nm CMOS process and occupies an ultra-compact active area of 0.000261 mm2, the smallest among the previously reported designs. At a 1.0 V supply voltage and 1 GS/s operation, the proposed ADC achieves an SNDR of 43.5 dB and dissipates 2.61 mW at the Nyquist rate, resulting in the state-of-the-art IRD of 470 TS/s $\cdot$ conv/mm2.

This letter presents a 4.5-to-14 GHz phase-locked loop (PLL)-based clock driver with wide-range 3-shaped LC-VCOs for GDDR6 DRAM test. We use two frequency modes to generate a write clock (WCK) from DC-to-14 GHz. In low-frequency mode under 4.5 GHz, the input from the automatic test equipment (ATE) is bypassed to WCK output. In high-frequency mode, PLL supports high-frequency WCK with good phase noise employing LC-VCOs. We propose 3 LC-VCOs to cover 48 frequency bands which support a frequency range from 4.5-to-14 GHz. Moreover, the current-mode driver with output common mode level control is proposed to provide programmability of the received clock input crossing point for the GDDR6 DRAM test. The prototype chip was fabricated in a 40 nm CMOS technology. The measured frequency tuning range is from 4.5-to-14 GHz with a tuning ratio of 102.7 %. The measured output common mode peak-to-peak difference is 200 mV. The measured integrated RMS jitter is 129 f_srms at 7 GHz, 180 fs_rms at 11 GHz, and 365 fs_rms at 14 GHz, respectively.

This article presents an energy-efficient voltage-mode transmitter with an unsegmented output driver that equalizes channel loss in the time domain based on the phase delay analysis. By modulating the phase of the transmitting clock rather than the serialized data stream, the proposed transmitter significantly reduces data-dependent jitter. The horizontal eye opening is improved by compensating for the zero-crossing time variation dependent on the run length of the transmitted data. The proposed scheme significantly reduces the driver complexity by eliminating many driver slices that consume large signaling and switching power. The prototype chip has been fabricated in a 28-nm CMOS process and occupies an active area of 0.045 mm ² . The measured results show that the proposed transmitter achieves an energy efficiency of 0.95 pJ/b at 22 Gb/s with an output swing of 440 mV _ppd at 1.0-V supply. In addition, peak-to-peak jitter is reduced from 34 to 20 ps at 22 Gb/s with the proposed phase delay compensation over the channel with a 15.0-dB loss.

This article proposes a deadzone-free clock and data recovery (CDR) without an external reference clock. To extract a frequency difference, the proposed referenceless CDR adopts a stochastic frequency detector, which utilizes consecutive data and edge samples. Although the probability-based frequency detection (FD) technique is promising, a deadzone should be carefully considered to prevent false locking. Therefore, by analyzing the stochastic FD thoroughly, this work proposes an autocovariance-based stochastic FD (ASFD) to resolve the deadzone issue and provide a more robust CDR operation. Since the autocovariance function is easily implemented in the digital domain, the proposed digital CDR with the ASFD improves the frequency tracking ability with minimal hardware overhead. Fabricated in 40-nm CMOS technology, the prototype CDR occupies an active area of 0.032mm². The CDR achieves a seamless frequency locking with a capture range from 14 to 32 Gb/s and frequency acquisition time within $7\mu$ s. At 32 Gb/s, the CDR achieves a bit error rate (BER) of less than $10{}^{-12}$ and an energy efficiency of 1.15 pJ/b at a supply voltage of 1.0 V.

The open source hardware movement has made significant progress over the past few years. Increasingly, more individuals are engaging with and participating in the open source chip design community, not only to design their chips with available open source tools but also to have their designs physically fabricated and returned to them for practical use. Companies like Google have sponsored physical chip fabrication runs over the past few years, such as OpenMPW, through semiconductor CMOS processes provided by Skywater (SKY130) and GlobalFoundries (GF180) [1]. When we consider the availability of open source chip design tools, a supportive community, reliable fabrication partners, financial sponsors, and a growing infrastructure of suppliers and educators, it becomes clear that a revolution in chip design is an inevitable outcome. By leveraging existing resources provided by the open source community, this article presents the joint development of a new laser-induced graphene (LIG)-based sensor platform. The effort includes the design, fabrication, and testing of an AFE ASIC using open tools and the design and in-house fabrication of LIG sensors. The article presents the ASIC’s design process and the fabricated chip’s testing results. It demonstrates testing a wearable strain gauge LIG sensor and a temperature-sensitive LIG sensor using our AFE chip. The demonstration serves as an example of the potential to develop the sensing system into a multimodal flexible sensing platform.

A balancing scheme for phase current and voltage of the flying capacitor in a fully integrated multi‐level multi‐phase DC–DC converter is proposed. The proposed balancing scheme based on the ripple voltage of the flying capacitor can simultaneously mitigate the imbalance of phase current and voltage of the flying capacitor. A mathematical analysis shows the proposed scheme can obtain the current information of the flying capacitor during charging and discharging operations and finally obtain the average inductor‐current value. A prototype 4‐phase 350 MHz three‐level DC–DC converter shows <4.7% voltage imbalance of the flying capacitor and <36 mA phase‐current imbalance at output voltage and maximum load current of 0.9 V and 1.2 A, respectively.

This brief presents a power- and area-efficient forwarded-clock (FC) receiver with a delay-locked loop (DLL)-based self-tracking loop for unmatched memory interfaces. In the proposed FC receiver, the self-tracking loop is composed of two-stage cascaded DLLs to support a burst mode. The proposed scheme compensates for a delay drift neither by relying on data (DQ) transitions nor by re-training but with a write training of the memory controller to fine-tune a data strobe (DQS) path delay through DLLs. The proposed FC receiver is fabricated in the 65-nm CMOS technology and the active area including 4 DQ lanes is 0.0329 mm ² . After the write training is completed at supply voltage of 1 V, the measured timing margin remains larger than 0.31 UI when the supply voltage drifts in the range of 0.94 V and 1.06 V from the training voltage, 1 V. At the data rate of 6.4 Gb/s, the proposed FC receiver achieves an energy efficiency of 0.45 pJ/bit.