A 1.62-8.1-Gb/s Single-loop Referenceless CDR with Fast Frequency Acquisition Technique for Embedded DisplayPort

A 25 Gb/s Energy-Efficient PAM-4 Receiver Utilizing a Pulse Amplitude Comparator and Modified Summation Method

An All-Digital Dual-Mode Clock and Data Recovery Circuit for Human Body Communication Systems

A power-saving control voltage-retention circuit for fast-locking phase-locked loops with sleep mode

A 0.6-V 4-MS/s Asynchronous SAR ADC With 2-bit Conversion/cycle Time-Domain Comparator

A Duty Cycle Corrector with Dual Loop Low Pass Filter for Low Jitter and Fast Correction Time

A 10-Bit 400-KS/s Low Noise Asynchronous SAR ADC with Dual-Domain Comparator for Input-Referred Noise Reduction

A Single-Ended Transmitter with Low Switching Noise Injection and Quadrature Clock Correction Schemes for DRAM Interface

A digital clock and data strobe aligner for write calibration of DRAM

On-chip Data Strobe Transmission with Short-Circuit Current Protection Scheme for DRAM