This article describes a multilevel hybrid plug-and-play dc–dc converter capable of converting a Li-ion battery input voltage range of 2.7–4.5 V to a system-on-chip voltage range of 0.6–1.3 V with an output spur as low as −53.5 dBm, a switching frequency variation of 0.13%, and peak efficiency of 88.6% at a corresponding power density of 0.061 W/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The converter, designed in 65-nm CMOS, uses a small 470-nH inductor and is stable with a multilayer ceramic output capacitor with only a 2-m <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\Omega$</tex-math></inline-formula> series resistance. A fully on-chip adaptive constant-on-time controller is employed, enabling a minimum efficiency of 70% for load currents as low as 30 mA with a response time of 3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula> s from a rapid 1-A load current step, without any need for external power supplies or control circuits.

This paper presents a DC-DC boost converter for energy harvesting. The time-domain maximum power point tracking (MPPT) technique implements to maximize the source's energy harvesting performance with no additional switch and time slot. Furthermore, it is implementing digital self-tracking zero current detectors (ST-ZCD) for high efficiency. This DC-DC boost converter fabricates with a 180nm CMOS process. The input voltage of the boost converter ranges from 0.2 to 0.7V and generates the output voltage of 1.2V. The total area of this converter with the MPPT operation is 600 μm x 475 μm. The measured power conversion efficiency of this DC-DC boost converter is 85.5%.

This article presents a power management integrated circuit for a wireless power receiver unit. A dual-mode high-efficiency active rectifier design is based on alliance for wireless power (A4WP) and wireless power consortium (WPC) standards. A gate charge recycling technique is proposed in the dual-mode active rectifier so that the current generated by the switching of the high side gate driver can be recycled to the rectifier output voltage in order to enhance efficiency. A step-down dc–dc converter with a proposed bootstrap circuit and dynamic pull-up resistor gate driver circuit is designed. The chip is implemented in a 0.18-μm bipolar-CMOS double-diffused metal-oxide-semiconductor process. The total die area, including the pad, is 2.64 mm × 2.6 mm. The measurement results show that the active rectifier achieves peak power conversion efficiency (PCE) of 94.7% and generates an output voltage of 7.68 V in WPC mode and 9.1 V with 93.4% efficiency in A4WPC mode. The input voltage varies from 10 V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P-P</sub> –12 V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P-P</sub> . Similarly, the step-down dc–dc converter obtains a peak PCE of 93.2% at a load current of 500 mA while producing an output voltage of 5 V. The overall system efficiency at A4WP and WPC mode are 86.7% and 88.2%, respectively.

This paper presents a comprehensive exploration of a Hybrid Energy Harvesting System designed to harvest energy from diverse sources, including 2.4 GHz and 5.8 GHz RF energy, electromagnetic (EM) energy, solar energy, and triboelectric energy. The proposed converter operates within a wide input voltage range, maximizing efficiency and stability. A reconfigurable RF-DC converter is used for both 2.4 GHz and 5.8 GHz frequencies to achieve high power conversion efficiency at low input power level. A maximum of 52 % and 44.8 % PCE is achieved at −14 dBm and −2 dBm respectively. Electromagnetic rectifier produces an output voltage of 1 V with a PCE of 95.6 % which operates with a 15 Hz input frequency. The voltage of the tribo rectifier is limited by the limiter circuit to 2.5 V with a PCE of 96 % concerning load current. A voltage combiner is used to combine all these harvested voltages and pass them to the buckboost DC-DC converter. This hybrid energy harvesting system is designed and fabricated in 180 nm bipolar-CMOSDMOS (BCD) technology with an active area of 2.8mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times 2.5$ </tex-math></inline-formula>mm. The buck-boost DC-DC converter incorporated into our hybrid energy harvesting system achieves an impressive peak Power Conversion Efficiency (PCE) of 95 %. This innovative system integrates EM, solar, triboelectric, and RF energy harvesters, collectively ensuring a reliable power source. The ultimate goal is to deliver a steady 5 V DC voltage, skillfully regulated by the buck-boost DC-DC converter.

This paper presents the design and performance evaluation of a fully integrated digital phased array-based nonlinear radar system. The proposed system employs a bi-static structure, where the transmitter and receiver are physically separated. The transmitter operates at 3–3.2 GHz, while the receiver is designed to capture the second harmonic responses at 6–6.4 GHz. The system consists of 64 channels for both transmission and reception, enabling electronic beam steering through phase shift control. To enhance the beamforming accuracy, a novel transmitter calibration method utilizing an oscilloscope instead of a network analyzer was implemented. The method simplifies synchronization requirements while maintaining precise phase alignment. Performance evaluation of the radar system was conducted through experimental validation in both free-space and concealed conditions, using arbitrary commercial electronic devices as targets. The experimental validation results demonstrated an average range error of 32.3 cm with a range resolution of 37.5 cm. Additionally, multi-target detection was performed using beamforming techniques. In free-space conditions, the radar achieved accurate target localization with angular errors below 1°. In concealed conditions, nonlinear reflections introduced minor localization errors due to clutter. Despite these challenges, the system successfully detected multiple targets by employing a clustering method. To the best of our knowledge, the system presented here is the first demonstration of a fully integrated digital phased array-based nonlinear radar in the open literature.

We propose a coupled transmission line (CTL)-based load network structure for the Doherty power amplifier (DPA) with an extended output power back-off (OBO) range, designed to achieve high efficiency and broad bandwidth. This load network features a highly simplified structure, consisting of a CTL and a post-matching network (PMN) with only two additional shunt elements. We also propose a novel approach to comprehensively analyze the CTL using its equivalent circuit model, which facilitates the comparison of various CTL-based load network structures suitable for DPA applications. By searching for 2-D closed-form parameters derived from the equivalent circuit models, we can determine the most suitable load network structure and its design parameters for optimal performance across a wide bandwidth. For implementation, a new method is proposed to ascertain the initial dimensions of a CTL based on analyzing the half-circuits as either a coplanar waveguide (CPW) or a CPW with a lower ground plane (CPWG), under even-mode and odd-mode conditions. To validate the proposed CTL-based load network and its equivalent circuit model, a DPA featuring an asymmetric structure using GaN-high electron mobility transistors (HEMTs) was designed and implemented, extending the back-off range to 8 dB for the broad frequency band, including the sub-6 5G (N78) band. The chosen load network, including the CTL, was fabricated on a two-layer printed circuit board (PCB). Measurement results show a drain efficiency (DE) of 44%–52.3% at an OBO of 8.0 dB from the saturated output power of approximately 43 dBm across the frequency range of 2.9–4.1 GHz under continuous wave (CW) signal excitation. With a 5G new radio (NR) signal featuring a bandwidth of 100 MHz and a peak-to-average power ratio (PAPR) of 7.8 dB, efficiencies of 48.0%–55.3% were achieved at an output power of 35.5 dBm, while maintaining an adjacent channel leakage power ratio (ACLR) of under −47.0 dBc across the frequency band after linearization using a digital pre-distortion (DPD) based on a memory polynomial.

A novel compact, high-gain, narrow-beam, broadband magnetoelectric (ME) dipole antenna is proposed for 60 GHz antenna-in-package (AiP) applications, specifically designed for ultra-high-speed, short-range communication. Initially, a ME dipole antenna was designed utilizing a high-permittivity single substrate layer, achieving significantly high gain, a narrow beam, and broad reflection bandwidth. Subsequently, a compact, low-loss substrate-integrated- waveguide (SIW) based differential power divider was developed on a low-permittivity substrate for effective integration and excitation of the proposed antenna in measurements. According to the measurement data, the antenna achieves a broad impedance bandwidth (IBW) of 25.2% (54.2–69.8 GHz) for \boldmath <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">|S_{11}|&amp;lt; </tex-math></inline-formula> –10 dB, with an ultra-narrow half-power beamwidth (HPBW) of less than 40<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${}^{\circ }$</tex-math></inline-formula> and remarkably high realized gain that ranges from 9.64 dBi to a peak value of 14.33 dBi. Furthermore, the antenna exhibits minimal cross-polarization, and a perfectly symmetrical radiation pattern, all attributed to its innovative complementary design.

This paper presents a bidirectional Four-Switch Buck-Boost (FSBB) converter with a high-voltage (HV) gate driver for use in power bank applications. The proposed FSBB is also integrated into this converter for increased efficiency. Thus, the proposed buck-boost converter can reduce conduction loss over a wide input voltage range by reducing the on-resistance of external MOSFETs using a gate source voltage (VGS) of 5V or 10V. The chip to be examined in this study is fabricated using a 130 nm 1P5M bipolar-CMOS-DMOS HV process with laterally diffused MOSFET (LDMOS) options to have a die size of 2.7 × 2.7 mm2. The proposed architecture is found to achieve a maximum output power level of 40W. The measurement results show that the maximum efficiencies at gate-source voltages (VGS) of 5V and 10V are 96.67% and 98.15%, respectively.

This article presents a boost converter based on a maximum power point tracking (MPPT) circuit, and a multicurrent detector (MCD), an offset cancellation circuit to achieve high efficiency over a wide range of input power. The proposed boost converter employs an MPPT design for adaptive on-time operation, which adjusts the on-time width to achieve maximum efficiency depending on the input voltage. In addition, a phase frequency detector-based offset cancellation method is proposed to minimize power loss by accurately sensing the current detector, thereby transferring power. Therefore, the proposed method achieves a significant efficiency improvement of up to 10 % by implementing high-precision offset cancellation with an offset level of approximately <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5\mu$ </tex-math></inline-formula>A, which is significantly lower than the conventional MCD offset of over 60 mA of maximum offset current level. The proposed boost converter fabricated in a 130 nm Bipolar-CMOS-DMOS (BCD) process occupies an active area of 0.806 mm2 and can self-start with a minimum input voltage of 450 mV (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$40\mu$ </tex-math></inline-formula>W) and achieve maximum efficiency of 92.7 %.

This article describes a multilevel hybrid plug-and-play dc–dc converter capable of converting a Li-ion battery input voltage range of 2.7–4.5 V to a system-on-chip voltage range of 0.6–1.3 V with an output spur as low as −53.5 dBm, a switching frequency variation of 0.13%, and peak efficiency of 88.6% at a corresponding power density of 0.061 W/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The converter, designed in 65-nm CMOS, uses a small 470-nH inductor and is stable with a multilayer ceramic output capacitor with only a 2-m <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\Omega$</tex-math></inline-formula> series resistance. A fully on-chip adaptive constant-on-time controller is employed, enabling a minimum efficiency of 70% for load currents as low as 30 mA with a response time of 3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula> s from a rapid 1-A load current step, without any need for external power supplies or control circuits.

This paper presents a DC-DC boost converter for energy harvesting. The time-domain maximum power point tracking (MPPT) technique implements to maximize the source's energy harvesting performance with no additional switch and time slot. Furthermore, it is implementing digital self-tracking zero current detectors (ST-ZCD) for high efficiency. This DC-DC boost converter fabricates with a 180nm CMOS process. The input voltage of the boost converter ranges from 0.2 to 0.7V and generates the output voltage of 1.2V. The total area of this converter with the MPPT operation is 600 μm x 475 μm. The measured power conversion efficiency of this DC-DC boost converter is 85.5%.