Design of High-Speed, Low-Power Sensing Circuits for Nano-Scale Embedded Memory

Bayesian Learning Automated SRAM Circuit Design for Power and Performance Optimization

High Efficiency Variation-Aware SRAM Timing Characterization via Machine Learning-Assisted Netlist Extraction

Cross-Coupled nFET Preamplifier for Low Voltage SRAM

Energy-Efficient Wide-Range Level Shifter With a Logic Error Detection Circuit

Voltage Boosted Fail Detecting Circuit for Selective Write Assist and Cell Current Boosting for High-Density Low-Power SRAM

Machine Learning-Based Read Access Yield Estimation and Design Optimization for High-Density SRAM

Design of Static Random-Access Memory Cell for Fault Tolerant Digital System

Self-Shut-Off Pulsed Latches for Minimizing Sequencing Overhead

광범위 저전력 동작을 위한 차동 전류 미러 기반 레벨 시프터