Mixed-signal Circuits and Systems Laboratory
서울시립대학교 본교(제1캠퍼스) 첨단융합학부
서민재 교수
SAR ADC
Noise-Shaping
SAR ADC
발행물
전체 논문
17
1
A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC
J.-H. Chung, Y.-D. Kim, C.-U. Park, K.-W. Park, D.-R. Oh, M.-J. Seo*, S.-T. Ryu*
IEEE J. Solid-State Circuits, 2024
2
Amorphous ITZO-Based Selector Device for Memristor Crossbar Array
K.-H. Kim, M.-J. Seo*, B.-C. Jang
MDPI Micromachines, 2023
3
A 7-bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique
D.-R. Oh, M.-J. Seo, S.-T. Ryu
IEEE J. Solid-State Circuits, 2022
4
A Single-Amplifier Dual-Residue Pipelined-SAR ADC
M.-J. Seo*
MDPI Electronics, 2021
5
A Single-Supply CDAC-Based Buffer-Embedding SAR ADC With Skip-Reset Scheme Having Inherent Chopping Capability
M.-J. Seo, D Jin, Y Kim, J Kim, S.-T. Ryu
IEEE J. Solid-State Circuits, 2020
6
A 40-nm CMOS 7-b 32-GS/s SAR ADC With Background Channel Mismatch Calibration
D.-S. Jo, B.-R.-S. Sung, M.-J. Seo, W.-C. Kim, S.-T. Ryu
IEEE Trans. Circuits Syst. II Express Briefs, 2020
7
A Reference-Free Temperature-Dependency-Compensating Readout Scheme for Phase-Change Memory Using Flash-ADC-Configured Sense Amplifiers
D.-H. Jin, J.-W. Kwon, M.-J. Seo, M.-Y. Kim, M.-C. Shin, S.-J. Kang, J.-H. Yoon, T.-S. Kim, S.-T. Ryu
IEEE J. Solid-State Circuits, 2019
8
A Reusable Code-based SAR ADC Design with CDAC Compiler and Synthesizable Analog Building Blocks
M.-J. Seo, Y.-J. Roh, D.-J. Chang, W. Kim, Y.-D. Kim, S.-T. Ryu
IEEE Trans. Circuits Syst. II Express Briefs., 2018
9
A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC
,
10
A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-μm CMOS
M.-J. Seo, D.-H. Jin, Y.-D. Kim, S.-I. Hwang, J.-P. Kim, S.-T. Ryu
IEEE Trans. Circuits Syst. II Express Briefs, 2018