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A 1.8V 128Mb Mobile DRAM with Triple Pumped VPP, Hybrid Current Sense Amplifier

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A 1.0V 256Mb SDRAM with offset-compensated direct sensing and charge-recycled precharge schemes

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Double boosting pump, hybrid current sense amplifier, and binary weighted temperature sensor adjustment schemes for 1.8V 128Mb mobile DRAMs

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A 4 Gb DDR SDRAM with gain-controlled pre-sensing and reference bitline calibration schemes in the twisted open bitline architecture

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840 Mb/s CMOS demultiplexed equalizing transceiver for DRAM-to processor communication