발행물
컨퍼런스
ICEIC 2025
2025
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A Hybrid Memory Device Combined with NAND Flash and DRAM
Stochastic Spiking Neuron with Controllable Probability for SNNs
An ADC-Free CMOS Neuron Based on Page Buffer
Capacitive Coupling-based Compute-In Memory Macro for Matrix-Vector Multiplication
IEEE Seoul Section Student Paper Contest
2024
Voltage-Summation-Based Compute-in-Memory Technology with Capacitive Synaptic Devices