INTELLIGENT CIRCUIT AND SYSTEM (ICS) DESIGN LAB
인하대학교 본교(제1캠퍼스) 반도체시스템공학과
변경수 교수
Low-Power Biomedical Microsystem Design
THz RF Circuit System Application Design
Machine Learning Circuit System Designs
발행물
전체 논문
71
61
Wireline/Wireless RF-Interconnect for Future SoC
R. Tam, F. Chang, J. Kim, G. Byun
IEEE International Symposium on RF Integration Technology, 2011
62
The DIMM Tree Architecture: A High Bandwidth and Scalable Memory System
Kanit T., G. Byun, J. Ir, G. Reinman, J. Cong, F. Chang
IEEE International Conference on Computer Design (ICCD), 2011
63
RF Interconnect Technology for On-chip and Off-chip Communication
J. Kim, G. Byun, F. Chang
Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD), 2011
64
An 8.4Gb/s 2.5pJ/b Mobile Memory I/O Interface Using Bi-directional and Simultaneous Dual (Base+RF)-Band Signaling
G. Byun, Y. Kim, J. Kim, R. Tam, J. Cong, G. Reinman, F. Chang
IEEE International Solid State Circuits Conference (ISSCC) Digest Technical Papers, 2011
65
A 5.0Gbps/Pin Packet-Based DRAM with Low Latency Receiver and Process Insensitive PLL
J. Choi, Y. Sohn, C. Kim, W. Park, J. Lee, U. Kang, G. Byun, I. Park, B. Kim, H. Hwang, C. Kim, S. Cho
IEEE Symposium on VLSI Circuits (VLSI) Digest Technical Papers, 2005
66
A 20GB/s 256MB DRAM with an Inductorless Quadrature PLL and a Cascaded Pre-emphasis Transmitter
K. Kim, Y. Sohn, C. Kim, G. Byun, H. Lee, J. Lee, J. Sunwoo, J. Choi, J. Chai, C. Kim, S. Cho
IEEE International Solid State Circuits Conference (ISSCC) Digest Technical Papers, 2005
67
A 512Mbit, 3.2Gbps/pin packet-based DRAM with cost-efficient clock generation and distribution scheme
Y. Sohn, J. Choi, I. Chung, C. Kim, G. Byun, D. Kang, W. Park, I. Park, H. Hwang, C. Kim, S. Cho
IEEE Symposium on VLSI Circuits (VLSI) Digest Technical Papers, 2004
68
A 1.8V 700Mb/s/Pin 512Mb DDR-II SDRAM with On-Die Termination and Off-Chip Driver Calibration
C. Yoo, G. Han, N. Heo, G. Byun, D. Lee, H. Choi, H. Kim, C. Kim, S. Cho
IEEE International Solid State Circuits Conference (ISSCC) Digest Technical Papers, 2003
69
A 1.2Gb/s /pin Double Data Rate SDRAM with On-Die-Termination
H. Song, J. Kwak, G. Byun, W. Lee, Y. Jun, S. Cho
IEEE International Solid State Circuits Conference (ISSCC) Digest Technical Papers, 2003
70
1.4 Gbps DLL Using 2nd Order Charge Pumping Scheme for Low Phase/Duty Error for High Speed DRAM Application
K. Kim, J. Lee, W. Lee, B. Jeong, G. Cho, J. Lee, G. Byun, C. Kim, Y. Jun, S. Cho
IEEE International Solid State Circuits Conference (ISSCC) Digest Technical Papers, 2004