A High-Speed Low-Complexity Reed-Solomon Decoder for Optical Communications

파이프라인 재귀적인 기술을 이용한 면적 효율적인 RS 복호기의 설계

VLSI Design of Digit-Serial FPGA Architecture

Pipelined Recursive Modified Euclidean Algorithm Block for Low-Complexity, High-Speed Reed-Solomon Decoder

High-Speed VLSI Architecture for Parallel Reed-Solomon Decoder

Performance Evaluation and Optimal Design for FPGA-Based Digit-Serial DSP Functions

FPGA-based digit-serial CSD FIR filter for image signal format conversion

Modified Euclidean Algorithm Block for High-Speed Reed-Solomon Decoder

A Comparative Study of Glitch-free TSPC D Flip-Flop

New XOR/XNOR and Full Adder Circuits for Low-Voltage, Low-Power Applications