The increasing demands of data‐centric applications continue to expose the fundamental bandwidth bottleneck of the von Neumann architecture, where memory and computation are separated. Analog processing‐in‐memory (PIM) offers a promising pathway to overcome this limitation, and charge‐trap flash (CTF) synapses stand out as attractive candidates owing to their scalability, multilevel storage, and complementary metal‐oxide‐semiconductor (CMOS) compatibility. In this work, a hardware‐level analog PIM system is presented that integrates CTF synapse arrays, CMOS‐based wordline drivers, and a novel successive integration‐and‐rescaling (SIR) neuron circuit in a chip‐on‐board configuration. Unlike conventional neuron designs that rely heavily on analog‐to‐digital conversion, the proposed SIR neuron performs bit‐sliced accumulation entirely in the analog domain. This architecture not only minimizes analog‐to‐digital converter overhead but also achieves excellent linearity through input‐node stabilization and functional capacitor separation, thereby enhancing both computational accuracy and area efficiency. The fabricated system is validated through handwritten digit classification on the modified national institute of standards and technology dataset, achieving an accuracy of 72.93%, which is only 3.91 percentage points lower than the software baseline under identical precision. These results underscore the pivotal role of the SIR neuron in bridging device‐level innovations with system‐level integration, positioning CTF‐based analog PIM as a scalable and energy‐efficient platform for neuromorphic computing.