Previous compute‐in‐memory (CIM) technologies use current summation for executing matrix–vector multiplication (MVM) operations and are gaining attention as next‐generation artificial intelligence (AI) computing systems. Despite their advantages, these technologies encounter significant difficulties, such as managing wide current ranges in large arrays, overcoming substantial “IR (current‐resistance)‐drop” issues, and integrating with complementary metal–oxide–semiconductor operating circuits. Herein, an innovative voltage‐summation‐based CIM (V‐CIM) technology is introduced; this technology represents a paradigm shift that employs capacitive coupling at a floating voltage summation node for MVM operations. By using a differential pair of input voltages (|Δ V |) with opposite signs relative to the reference voltage, the accumulated MVM results at the floating summation node cancel out, eliminating IR‐drop. Representing the MVM result as an analog voltage simplifies the neuron circuit design and significantly reduces energy consumption. V‐CIM technology is reported with two types of capacitive synaptic devices: read‐only and programmable. A prototype V‐CIM chip using read‐only capacitors is developed, demonstrating the superiority of V‐CIM in image classification applications. For programmable capacitive synaptic devices, a memcapacitor device based on logic‐compatible embedded flash memory is introduced. The work sheds light on ultralow‐power, highly integrated, and highly reliable AI computing systems based on CIM technology.

The increasing demands of data‐centric applications continue to expose the fundamental bandwidth bottleneck of the von Neumann architecture, where memory and computation are separated. Analog processing‐in‐memory (PIM) offers a promising pathway to overcome this limitation, and charge‐trap flash (CTF) synapses stand out as attractive candidates owing to their scalability, multilevel storage, and complementary metal‐oxide‐semiconductor (CMOS) compatibility. In this work, a hardware‐level analog PIM system is presented that integrates CTF synapse arrays, CMOS‐based wordline drivers, and a novel successive integration‐and‐rescaling (SIR) neuron circuit in a chip‐on‐board configuration. Unlike conventional neuron designs that rely heavily on analog‐to‐digital conversion, the proposed SIR neuron performs bit‐sliced accumulation entirely in the analog domain. This architecture not only minimizes analog‐to‐digital converter overhead but also achieves excellent linearity through input‐node stabilization and functional capacitor separation, thereby enhancing both computational accuracy and area efficiency. The fabricated system is validated through handwritten digit classification on the modified national institute of standards and technology dataset, achieving an accuracy of 72.93%, which is only 3.91 percentage points lower than the software baseline under identical precision. These results underscore the pivotal role of the SIR neuron in bridging device‐level innovations with system‐level integration, positioning CTF‐based analog PIM as a scalable and energy‐efficient platform for neuromorphic computing.

Studies on neuromorphic computing systems are becoming increasingly important in the big-data-processing era as these systems are capable of energy-efficient parallel data processing and can overcome the present limitations owing to the von Neumann bottleneck. The Pt/WO x /ITO resistive random-access memory device can be used to implement versatile synapse functions because it possesses both volatile and nonvolatile characteristics. The gradual increase and decrease in the current of the Pt/WO x /ITO device with its uniform resistance state for endurance and retention enables additional synaptic applications that can be controlled using electric pulses. If the volatile and nonvolatile device properties are set through rehearsal and forgetting processes, the device can emulate various synaptic behaviors, such as potentiation and depression, paired-pulse facilitation, post-tetanic potentiation, image training, Hebbian learning rules, excitatory postsynaptic current, and Pavlov’s test. Furthermore, reservoir computing can be implemented for applications such as pattern generation and recognition. This emphasizes the various applications of future neuromorphic devices, demonstrating the various favorable characteristics of pulse-enhanced Pt/WO x /ITO devices.

The increasing demands of data‐centric applications continue to expose the fundamental bandwidth bottleneck of the von Neumann architecture, where memory and computation are separated. Analog processing‐in‐memory (PIM) offers a promising pathway to overcome this limitation, and charge‐trap flash (CTF) synapses stand out as attractive candidates owing to their scalability, multilevel storage, and complementary metal‐oxide‐semiconductor (CMOS) compatibility. In this work, a hardware‐level analog PIM system is presented that integrates CTF synapse arrays, CMOS‐based wordline drivers, and a novel successive integration‐and‐rescaling (SIR) neuron circuit in a chip‐on‐board configuration. Unlike conventional neuron designs that rely heavily on analog‐to‐digital conversion, the proposed SIR neuron performs bit‐sliced accumulation entirely in the analog domain. This architecture not only minimizes analog‐to‐digital converter overhead but also achieves excellent linearity through input‐node stabilization and functional capacitor separation, thereby enhancing both computational accuracy and area efficiency. The fabricated system is validated through handwritten digit classification on the modified national institute of standards and technology dataset, achieving an accuracy of 72.93%, which is only 3.91 percentage points lower than the software baseline under identical precision. These results underscore the pivotal role of the SIR neuron in bridging device‐level innovations with system‐level integration, positioning CTF‐based analog PIM as a scalable and energy‐efficient platform for neuromorphic computing.

Previous compute‐in‐memory (CIM) technologies use current summation for executing matrix–vector multiplication (MVM) operations and are gaining attention as next‐generation artificial intelligence (AI) computing systems. Despite their advantages, these technologies encounter significant difficulties, such as managing wide current ranges in large arrays, overcoming substantial “IR (current‐resistance)‐drop” issues, and integrating with complementary metal–oxide–semiconductor operating circuits. Herein, an innovative voltage‐summation‐based CIM (V‐CIM) technology is introduced; this technology represents a paradigm shift that employs capacitive coupling at a floating voltage summation node for MVM operations. By using a differential pair of input voltages (|Δ V |) with opposite signs relative to the reference voltage, the accumulated MVM results at the floating summation node cancel out, eliminating IR‐drop. Representing the MVM result as an analog voltage simplifies the neuron circuit design and significantly reduces energy consumption. V‐CIM technology is reported with two types of capacitive synaptic devices: read‐only and programmable. A prototype V‐CIM chip using read‐only capacitors is developed, demonstrating the superiority of V‐CIM in image classification applications. For programmable capacitive synaptic devices, a memcapacitor device based on logic‐compatible embedded flash memory is introduced. The work sheds light on ultralow‐power, highly integrated, and highly reliable AI computing systems based on CIM technology.

Studies on neuromorphic computing systems are becoming increasingly important in the big-data-processing era as these systems are capable of energy-efficient parallel data processing and can overcome the present limitations owing to the von Neumann bottleneck. The Pt/WO x /ITO resistive random-access memory device can be used to implement versatile synapse functions because it possesses both volatile and nonvolatile characteristics. The gradual increase and decrease in the current of the Pt/WO x /ITO device with its uniform resistance state for endurance and retention enables additional synaptic applications that can be controlled using electric pulses. If the volatile and nonvolatile device properties are set through rehearsal and forgetting processes, the device can emulate various synaptic behaviors, such as potentiation and depression, paired-pulse facilitation, post-tetanic potentiation, image training, Hebbian learning rules, excitatory postsynaptic current, and Pavlov’s test. Furthermore, reservoir computing can be implemented for applications such as pattern generation and recognition. This emphasizes the various applications of future neuromorphic devices, demonstrating the various favorable characteristics of pulse-enhanced Pt/WO x /ITO devices.

Spiking neural networks (SNNs) have been researched as an alternative to reduce the gap with the human brain in terms of energy efficiency, due to their inherent spare event‐driven characteristics from a hardware implementation perspective. However, they still face significant challenges in learning, compared to artificial neural networks (ANNs). Recently, several algorithms have been developed to narrow the performance gap between SNNs and ANNs, including features in spiking neurons that can reduce information loss in the membrane potential. Inspired by these advancements, the current study designs and measures a neuron circuit using 180 nm complementary metal‐oxide‐semiconductor (CMOS) technology to address this information loss. The proposed circuit successfully implements these features, and their performance is validated through simulation based on the measured data.

Advancements in semiconductor technology have significantly improved the performance of DRAM and NAND flash, establishing them as high-speed main memory and high-capacity storage, respectively. However, the persistent performance gap between these two memory types remains a critical bottleneck in modern computing systems. To address this challenge, we propose a hybrid memory architecture, termed NAD, which tightly integrates DRAM and NAND flash to enable direct and parallel data transfer. By eliminating intermediate components such as I/O buffers and data buses typically used for inter-memory communication, the proposed NAD architecture significantly reduces data transfer latency. To validate its functionality, NAD memory was fabricated using a TSMC 180 nm CMOS logic process. Experimental results confirm reliable data transfer between DRAM and NAND flash, demonstrating the feasibility of NAD as a promising solution for overcoming memory bottlenecks in next-generation computing systems.

Matrix-vector multiplication (MVM) is a core operation in large language models (LLMs), and compute-inmemory (CIM) technologies offer a promising path to overcome data movement bottlenecks. Among them, capacitive coupling principle-based CIM (CCP-CIM) enables low-power operation by eliminating static current paths. In this work, we propose an energy-efficient neuron circuit optimized for CCPCIM. The design features a cascaded input stage for enhanced transconductance linearity, as well as feedback-assisted control and overflow/underflow detection to reduce unnecessary digital conversions. Furthermore, the discharge rate is dynamically adjustable through analog biasing, enabling flexible control of the neuron’s response range. Implemented in TSMC 28 nm CMOS, the proposed design achieves up to 2.15× less energy consumption than a conventional neuron circuit. This work supports scalable and adaptive analog inference for edge AI applications.

In this study, we propose a 9×10 neuromorphic architecture that utilizes stochastic spiking neurons and SRAM as synapses. The stochastic spiking neuron features a capacitor-less structure, reducing hardware complexity and enabling low-power operation. Additionally, binary SRAM is employed as synapses to further enhance low-power characteristics. The proposed architecture was fabricated using the TSMC 28nm CMOS process. Simulation results confirm that the proposed design achieves a high energy efficiency of 60.55 TOPS/W. Through this approach, we aim to develop a low-power artificial neural network suitable for edge devices.