발행물

전체 논문

61

31

A Simple Static Noise Margin Model of MOS CML Gate in CMOS Processes
Hocheol Jeong, Jaehyun Kang, Kang-Yoon Lee, Minjae Lee
Journal of Semiconductor and Technology Science(JSTS), 2017.06

32

Fractional spur reduction technique using 45° phase dithering in phase interpolator based all-digital phase-locked loop
Junsoo Ko, Minuk Heo, Jayeol Lee, Cheon-Soo Kim, Minjae Lee
Electronics Letters, 2016.11

33

A Wide Input Range, 95.4% Power Efficiency DC-DC Buck Converter with a Phase-locked Loop in 0.18 μm BCD
Hongjin Kim, Young-Jun Park, Ju-Hyun Park, Ho-Cheol Ryu, Young-Gun Pu, Minjae Lee, Keumcheol Hwang, Younggoo Yang, Kang-Yoon Lee
Journal of Power Electronics, 2016.11

34

A 12 bit 250 MS/s 28 mW +70 dB SFDR non-50% RZ DAC in 0.11 μm CMOS using controllable RZ window for wireless SoC integration
Seonggeon Kim, Jaehyun Kang, Minjae Lee
Microelectronics Journal, 2016.10

35

A 1.1V 10-bit 62MS/s pipeline ADC with two-step non-overlapping clock generation for multi I-Q channel RF receivers
Hyungyu Ju, Minjae Lee
Analog Integrated Circuits and Signal Processing, 2016.06

36

Design of 12-phase, 2-stage Harmonic Rejection Mixer for TV Tuners
Dongju Lee, Hocheol Jeong, Minjae Lee
Radioengineering, 2016.06

37

Low Flicker Noise, Odd-Phase Master LO Active Mixer Using a Low Switching Frequency Scheme
Dongju Lee, Minjae Lee
IEEE J. Solid-State Circuits, 2015.10

38

Low-power programmable high-gain time difference amplifier with regeneration time control
Minuk Heo, Daehyeon Kwon, Minjae Lee
Electron. Lett., 2014.07

39

A Semi-Blind Digital-Domain Calibration of Pipelined A/D Converters via Convex Optimization
Jintae Kim, Minjae Lee
IEEE Transactions on VLSI Systems, 2015.07

40

Asymmetric monotonic switching scheme for energy-efficient SAR ADCs
Hyeonho Song, Minjae Lee
IEICE Electronics Express, 2014.06