Solution-processed tin (Sn2+)-halide perovskites can be used to create p-channel thin-film transistors (TFTs) with performance levels comparable with commercial low-temperature polysilicon technology. However, high-quality perovskite film deposition using industry-compatible production techniques remains challenging. Here we report the fabrication of p-channel Sn2+-halide perovskite TFTs using a thermal evaporation approach with inorganic caesium tin iodide (CsSnI3). We use lead chloride (PbCl2) as a reaction initiator that triggers solid-state reactions of the as-evaporated perovskite compounds. This promotes the conversion of dense and uniform perovskite films, and also modulates the intrinsically high hole density of the CsSnI3 perovskite channels. Our optimized TFTs exhibit average hole field-effect mobilities of around 33.8 cm2 V−1 s−1, on/off current ratios of around 108, and large-area fabrication uniformity. The devices also exhibit improved stability compared with solution-deposited devices. Using a thermal evaporation approach and lead chloride (PbCl2) as a reaction initiator, caesium tin iodide (CsSnI3)-based p-channel thin-film transistors can be fabricated that exhibit average hole field-effect mobilities of around 33.8 cm2 V−1 s−1 and improved stability compared with solution-deposited devices.

Compared to polycrystalline semiconductors, amorphous semiconductors offer inherent cost-effective, simple and uniform manufacturing. Traditional amorphous hydrogenated Si falls short in electrical properties, necessitating the exploration of new materials. The creation of high-mobility amorphous n-type metal oxides, such as a-InGaZnO (ref. ¹), and their integration into thin-film transistors (TFTs) have propelled advancements in modern large-area electronics and new-generation displays^2-8. However, finding comparable p-type counterparts poses notable challenges, impeding the progress of complementary metal-oxide-semiconductor technology and integrated circuits^9-11. Here we introduce a pioneering design strategy for amorphous p-type semiconductors, incorporating high-mobility tellurium within an amorphous tellurium suboxide matrix, and demonstrate its use in high-performance, stable p-channel TFTs and complementary circuits. Theoretical analysis unveils a delocalized valence band from tellurium 5p bands with shallow acceptor states, enabling excess hole doping and transport. Selenium alloying suppresses hole concentrations and facilitates the p-orbital connectivity, realizing high-performance p-channel TFTs with an average field-effect hole mobility of around 15 cm² V^-1 s^-1 and on/off current ratios of 10⁶-10⁷, along with wafer-scale uniformity and long-term stabilities under bias stress and ambient ageing. This study represents a crucial stride towards establishing commercially viable amorphous p-channel TFT technology and complementary electronics in a low-cost and industry-compatible manner.

Ligand exchange of perovskite nanocrystals (PNCs) is an essential process for optoelectronics applications, but it often causes structural instability and degradation of PNCs. In this work, we demonstrate that PNCs synthesized via ligand-assisted reprecipitation (LARP) using a liquid crystalline (LC) antisolvent, referred to as LC-LARP, enable a significantly more efficient and stable ligand-exchange process compared with those prepared by conventional LARP using toluene (T-LARP). After ligand exchange, PNCs from the LC-LARP (LC-PNCs) exhibit a dramatic increase in photoluminescence quantum yield (PLQY) from 29% to 80%, whereas PNCs from T-LARP (T-PNCs) show negligible improvement. Furthermore, LC-PNCs show exceptional stability under ligand-exchange reactions, retaining over 50% PLQY even at high ligand concentrations that trigger the complete decomposition of T-PNCs. This efficient and stable ligand exchange is attributed to superior ligand passivation and a low density of surface defects in LC-PNCs. Our approach is versatile and generalizable across diverse ligands and perovskite compositions. Finally, we demonstrate the practical utility of this method by designing LC-PNC-based light-emitting diodes (LEDs), which achieve a maximum external quantum efficiency (8.2%), significantly surpassing that of T-PNC-based LEDs (0.5%).

ABSTRACT The development of high‐performance p‐type 2D transistors is hindered by Fermi level pinning (FLP) caused by the direct deposition of the contact metal on the 2D semiconducting layer, resulting in a Schottky barrier that limits efficient hole injection. In this study, we demonstrate a contact engineering strategy that enhances the p‐type 2D transistor performance by inserting a selenium interlayer (SIL) between the contact metal and transition metal dichalcogenide (TMD). Utilizing the physics of Fermi level pinning, we optimize the Fermi level to deeper levels at the metal‐selenium interface, enhancing hole injection. Through SIL insertion, the average hole field‐effect mobility of WSe 2 transistors increases significantly from 23 to 107 cm 2 V −1 s −1 , and the on‐current density from 8.4 to 55 µA/µm. The on/off current ratio exceeds 10 8 , and the maximum mobility reaches 119 cm 2 V −1 s −1 . The effectiveness of this approach is demonstrated in various p‐type TMD channels, including WSe 2 , WS 2 , and MoSe 2, as well as in various metal electrodes, all of which exhibit enhanced hole injection. This work provides a simple method to enhance the performance of p‐type 2D transistors by improving the hole injection efficiency.

Intrinsically stretchable electronics is rapidly emerging as a transformative platform for next-generation electronics, offering novel form factors and enhanced capabilities. Herein, we report high-performance intrinsically stretchable thin-film transistors based on two-dimensional semiconducting flakes. Our n-type molybdenum disulfide transistors exhibit a maximum field-effect mobility up to 12.5 cm²V^-1s^-1 (average 8 cm²V^-1s^-1) and an on/off current ratio above 10⁷, even under 20% strain, and demonstrate stable performance during cyclic stretching tests. Structural analysis revealed that mechanical strain was accommodated via interflake motions; the flakes are connected by weak van der Waals bonds, enabling effective stress relaxation within the transistor channel. Furthermore, charge transport from the source to the drain in the channel remains robust as long as the vertical interconnection between the flakes and the substrate is maintained under stretching. This strain accommodation mechanism offers a generalizable pathway for integrating van der Waals semiconductors into stretchable electronics and addresses the critical lack of high-performance stretchable n-type materials for complementary metal-oxide-semiconductor integration, paving the way for logically capable and scalable deformable systems.

Solution-processed tin (Sn2+)-halide perovskites can be used to create p-channel thin-film transistors (TFTs) with performance levels comparable with commercial low-temperature polysilicon technology. However, high-quality perovskite film deposition using industry-compatible production techniques remains challenging. Here we report the fabrication of p-channel Sn2+-halide perovskite TFTs using a thermal evaporation approach with inorganic caesium tin iodide (CsSnI3). We use lead chloride (PbCl2) as a reaction initiator that triggers solid-state reactions of the as-evaporated perovskite compounds. This promotes the conversion of dense and uniform perovskite films, and also modulates the intrinsically high hole density of the CsSnI3 perovskite channels. Our optimized TFTs exhibit average hole field-effect mobilities of around 33.8 cm2 V−1 s−1, on/off current ratios of around 108, and large-area fabrication uniformity. The devices also exhibit improved stability compared with solution-deposited devices. Using a thermal evaporation approach and lead chloride (PbCl2) as a reaction initiator, caesium tin iodide (CsSnI3)-based p-channel thin-film transistors can be fabricated that exhibit average hole field-effect mobilities of around 33.8 cm2 V−1 s−1 and improved stability compared with solution-deposited devices.

Compared to polycrystalline semiconductors, amorphous semiconductors offer inherent cost-effective, simple and uniform manufacturing. Traditional amorphous hydrogenated Si falls short in electrical properties, necessitating the exploration of new materials. The creation of high-mobility amorphous n-type metal oxides, such as a-InGaZnO (ref. ¹), and their integration into thin-film transistors (TFTs) have propelled advancements in modern large-area electronics and new-generation displays^2-8. However, finding comparable p-type counterparts poses notable challenges, impeding the progress of complementary metal-oxide-semiconductor technology and integrated circuits^9-11. Here we introduce a pioneering design strategy for amorphous p-type semiconductors, incorporating high-mobility tellurium within an amorphous tellurium suboxide matrix, and demonstrate its use in high-performance, stable p-channel TFTs and complementary circuits. Theoretical analysis unveils a delocalized valence band from tellurium 5p bands with shallow acceptor states, enabling excess hole doping and transport. Selenium alloying suppresses hole concentrations and facilitates the p-orbital connectivity, realizing high-performance p-channel TFTs with an average field-effect hole mobility of around 15 cm² V^-1 s^-1 and on/off current ratios of 10⁶-10⁷, along with wafer-scale uniformity and long-term stabilities under bias stress and ambient ageing. This study represents a crucial stride towards establishing commercially viable amorphous p-channel TFT technology and complementary electronics in a low-cost and industry-compatible manner.