Dynamic Optimization of Hessian Determinant Image Pyramid for Memory-Efficient and High Performance Keypoint Detection in SURF

Efficient Reconfigurable Architecture to Accelerate Descriptor Extraction in SURF Algorithm

Reconfigurable Hardware Architecture for Faster Descriptor Extraction in SURF

Inter-CGRA Reconfiguration Technique for Efficient Pipelining of Kernel Stream on CGRA-based Multi-Core Architecture

Dynamic Redundancy-based Fault-Recovery Scheme for Reliable CGRA-based Multi-Core Architecture

Efficient Fault-Recovery Technique for CGRA-based Multi-Core Architecture

Energy-Efficient and High Performance CGRA-based Multi-Core Architecture

Power-Efficient Configuration Cache Structure for Coarse-Grained Reconfigurable Architecture

Hierarchical Multiplexing Interconnection Structure for Fault-Tolerant Reconfigurable Chip Multiprocessor

Reconfigurable Multi-Array Architecture for Low-Power and High-Speed Embedded Systems