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51
Maximizing SIMD Resource Utilization in GPGPUs with SIMD Lane Permutation
Minsoo Rhu, Mattan Erez
2013
52
The Dual-Path Execution Model for Efficient GPU Control Flow
Minsoo Rhu, Mattan Erez
2013
53
CAPRI: Prediction of Compaction-Adequacy for Handling Control-Divergence in GPGPU Architectures
Minsoo Rhu, Mattan Erez
2012
54
Optimization of Arithmetic Coding for JPEG2000
Minsoo Rhu, In-Cheol Park
IEEE Transactions on Circuits and System for Video Technology, 2010
55
Memory-less Bit-Plane Coder Architecture for JPEG2000 with Concurrent Column-Stripe Coding
Minsoo Rhu, In-Cheol Park
IEEE International Conference on Image Processing 2009 (ICIP 2009), 2009
56
Architecture Design of a High-Performance Dual-Symbol Binary Arithmetic Coder for JPEG2000
Minsoo Rhu, In-Cheol Park
IEEE International Conference on Image Processing 2009 (ICIP 2009), 2009
57
A Novel Trace-Pipelined Binary Arithmetic Coder Architecture for JPEG2000
Minsoo Rhu, In-Cheol Park
IEEE Workshop on Signal Processing Systems 2009 (SiPS 2009), 2009
58
A Characterization of Generative Recommendation Models: Study of Hierarchical Sequential Transduction Unit
Rhu, Minsoo, Kim, Taehun, Lee, Yunjae, Lim, Juntaek
IEEE COMPUTER ARCHITECTURE LETTERS, 2025
59
Characterization and Analysis of the 3D Gaussian Splatting Rendering Pipeline
Rhu, Minsoo, Lee, Jiwon, Lee, Yunjae, Kwon, Youngeun
IEEE COMPUTER ARCHITECTURE LETTERS, 2025
60
Characterization and Analysis of Text-to-Image Diffusion Models
Bang, Jehyeon, Rhu, Minsoo, Cho, Eunyeong
IEEE COMPUTER ARCHITECTURE LETTERS, 2024
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