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International SoC Design Conference
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A Digital PWCL for Multi-Phase Clock Applications
International Technical Conference on Circuits/Systems, Computers and Communications
A CMOS Multi-phase Delay-Locked Loop for storage media using a 0.18-um CMOS Process
IEEE International Solid State Circuit Conference
A 3Gb/s 8b Single-Ended Transceiver for 4-drop DRAM Interface with Digital Calibration of Equalization, Skew and Offset Coefficients
A 4-Gb/s Single-Ended Transmitter for DRAM Interface with Pre-Emphasis and Low Skew Multiplexing using a 0.25um CMOS Process
Extraction of SPICE Parameters for Through-Hole Via Using a Regular VNA Measurement on Via-TL-Via Structure for Use in DRAM DIMM Modeling