,

A 1.2Gbps CMOS DFE Receiver with the Extended Sampling Time Window for Application to the SSTL Channel

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An improved algorithm of DC operating point computation for CMOS VLSI circuit simulation with an improvement factor between 40% and 80% over commercial SPICE programs

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ABCD matrix를 이용한 DRAM BUS 채널의 빠른 분석 방법

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Adaptive Reference 기법을 이용한 DRAM 버스용 1.6Gbps CMOS 수신 회로

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A High-Speed CMOS Divide-by-N Counter with Simplified Counter Flip-Flops