Implementation of asynchronous reorder buffer for asynchronous on-chip bus

Parallel 4x4 transform architecture based on bit extended arithmetic for H. 264/AVC

Reconfigurable Co-synthesis System Architecture

Differential value encoding for delay insensitive handshake protocol

Asynchronous Reorder Buffer for Multiple Outstanding Transactions on Asynchronous On-Chip Bus

Low delay-power product current-mode multiple valued logic for delay-insensitive data transfer mechanism

High performance asynchronous on-chip bus with multiple issue and out-of-order/in-order completion

Special Section on Cryptography and Information Security-LETTERS-An Area Efficient Approach to Design Self-Timed Cryptosystems Combatting DPA Attack

Design of Low Powered Delay Insensitive Data Transfers based on Current-Mode Multiple Valued Logic

Special Section on Recent Advances in Circuits and Systems--Part 1-Communications and Wireless Systems-Differential Value Encoding for Delay Insensitive Handshake Protocol