발행물

전체 논문

354

1

Performance and area scaling benefits of FD-SOI technology for 6-T SRAM cells at the 22-nm node
Shin, C., Cho, M. H., Tsukamoto, Y., Nguyen, B. Y., Mazure, C., Nikolic, B., Liu, T. J. K.
IEEE Transactions on electron devices, 2010

2

Performance and yield benefits of quasi-planar bulk CMOS technology for 6-T SRAM at the 22-nm node
Shin, C., Damrongplasit, N., Sun, X., Tsukamoto, Y., Nikolic, B., Liu, T. J. K.
IEEE transactions on electron devices, 2011

3

Quasi-planar bulk CMOS technology for improved SRAM scalability
Shin, C., Tsai, C. H., Wu, M. H., Chang, C. F., Liu, Y. R., Kao, C. Y., ..., Liu, T. J. K.
Solid-state electronics, 2011

4

Design optimization of multigate bulk MOSFETs
Ho, B., Sun, X., Shin, C., Liu, T. J. K.
IEEE transactions on electron devices, 2012

5

Effect of double-patterning and double-etching on the line-edge-roughness of multi-gate bulk MOSFETs
Park, I. J., Shin, C.
IEICE Electronics Express, 2013

6

Study of high-k/metal-gate work-function variation using Rayleigh distribution
Nam, H., Shin, C.
IEEE Electron Device Letters, 2013

7

The design optimization and variation study of segmented-channel MOSFET using HfO 2 or SiO 2 trench isolation
Nam, H., Shin, C.
2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2013

8

Impact of Using Double-Patterning Versus Single-Patterning on Threshold Voltage $(V\_ {\rm TH}) $ Variation in Quasi-Planar Tri-Gate Bulk MOSFETs
Shin, C., Park, I. J.
IEEE electron device letters, 2013

9

Comparative study in work-function variation: Gaussian vs. Rayleigh distribution for grain size
Nam, H., Shin, C.
IEICE Electronics Express, 2013

10

Monte Carlo Simulation Study: the effects of double-patterning versus single-patterning on the line-edge-roughness (LER) in FDSOI Tri-gate MOSFETs
Park, I. J., Shin, C.
JSTS: Journal of Semiconductor Technology and Science, 2013