Zero-Sleep-Leakage Flip-Flop Circuit With Conditional-Storing Memristor Retention Latch

SPICE Macromodel and CMOS Emulator for Memristors

Compact Verilog-A model of phase-change ram transient behaviors for multi-level applications

Carry select adder with sub-block power gating for reducing active-mode leakage in sub-32-nm VLSIs

Compact and efficient Maximum Power Point Tracking circuit for portable solar battery charger

Oxide-tunneling leakage suppressed SRAM for sub-65-nm Very Large Scale Integrated circuits

Dual-switch power gating revisited for small sleep energy loss and fast wake-up time in sub-45-nm nodes

Self-adaptive write circuit for low-power and variation-tolerant memristors

Design of gate stacks for improved program/erase speed, retention and process margin aiming next generation metal nanocrystal memories

A compact Verilog-A model for Multi-Level-Cell Phase-change RAMs