Low-power read circuit with self-adjusted column pulse width for diode-switch resistive RAMs

Negative charge pump circuit with large output current and high power efficiency

Sub-1-V-Output CMOS bandgap reference circuit with small area and low power consumption

Sence amplifier driving scheme with adaptive delay line for reducing peak current and driving time variations in deep-sub-micron DRAMs

Comparative Study on Leakage Current of power-gated SRAMs for 65-nm, 45-nm, and 32-nm technology nodes

A modified dickson charge pump circuit with high efficiency and high output voltage

Sense amplifier driving scheme with adaptive delay line for reducing peak current and driving time variations in deep-sub-micron DRAMs

A compact HSPICE macromodel of resistive RAM

Fast-delay and low-power level shifter for low-voltage applications

Leakage-suppressed clock-gating circuit with zigzag super cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-VDD LSIs