This article describes a single-ended (SE) clock-referenced PAM3 (CR-PAM3) transceiver that achieves an energy efficiency of 0.275 pJ/b at a high data rate of 42 Gb/s. The proposed CR-PAM3 signaling provides tolerance to supply noise and reference offset in SE chiplet or die-to-die (D2D) interfaces by using forwarded clock as reference voltages instead of generating them at the RX side. To minimize power consumption for PAM3, a differentially weighted data driver is employed. The proposed XTC-combined FS-puller helps voltage level transition while canceling FEXT from adjacent channels. A decision feedback equalizer (DFE)-embedded sampler enables low-power feedback within 1 UI by eliminating the CML summer structure and directly adding a tap branch to the sampler. A digital on-chip foreground training sequence is used to sequentially train TX per-lane deskew, clock swing level, and RX quadrature error corrector (QEC). Six data lanes, two clock lanes, and one replica lane for testing are implemented using an on-chip 2-mm channel in a 28-nm CMOS technology. In the presence of 200-mVpp 120-MHz sinusoidal supply noise injected at TX, horizontal and vertical eyes with CR-PAM3 are measured as 0.34 UI and 121 mV at BER <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$<10^{-12}$</tex-math> </inline-formula>, while the conventional PAM3 eye is closed.

This article presents design techniques for an energy-efficient multi-lane receiver (RX) with baud-rate clock and data recovery (CDR), which is essential for high-throughput low-latency communication in high-performance computing systems. The proposed low-power global clock distribution not only significantly reduces power consumption across multi-lane RXs but is capable of compensating for the frequency offset without any phase interpolators (PIs). To this end, a fractional divider (FDIV) controlled by CDR is placed close to the global phase locked loop. Moreover, in order to address the suboptimal lock point of conventional baud-rate phase detectors, the proposed CDR employs a background eye-climbing algorithm (ECA), which optimizes the sampling phase and maximizes the vertical eye margin (VEM). Fabricated in a 28 nm CMOS process, the proposed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times 32$ </tex-math></inline-formula> Gb/s RX shows a low integrated fractional spur of −40.4 dBc at a 2500 ppm frequency offset. Furthermore, it improves bit-error-rate (BER) performance by increasing the VEM by 26 mV. The entire RX achieves the energy efficiency of 1.8 pJ/bit with the aggregate data rate of 128 Gb/s.

This article describes a single-ended (SE) clock-referenced PAM3 (CR-PAM3) transceiver that achieves an energy efficiency of 0.275 pJ/b at a high data rate of 42 Gb/s. The proposed CR-PAM3 signaling provides tolerance to supply noise and reference offset in SE chiplet or die-to-die (D2D) interfaces by using forwarded clock as reference voltages instead of generating them at the RX side. To minimize power consumption for PAM3, a differentially weighted data driver is employed. The proposed XTC-combined FS-puller helps voltage level transition while canceling FEXT from adjacent channels. A decision feedback equalizer (DFE)-embedded sampler enables low-power feedback within 1 UI by eliminating the CML summer structure and directly adding a tap branch to the sampler. A digital on-chip foreground training sequence is used to sequentially train TX per-lane deskew, clock swing level, and RX quadrature error corrector (QEC). Six data lanes, two clock lanes, and one replica lane for testing are implemented using an on-chip 2-mm channel in a 28-nm CMOS technology. In the presence of 200-mVpp 120-MHz sinusoidal supply noise injected at TX, horizontal and vertical eyes with CR-PAM3 are measured as 0.34 UI and 121 mV at BER <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$<10^{-12}$</tex-math> </inline-formula>, while the conventional PAM3 eye is closed.

This article presents design techniques for an energy-efficient multi-lane receiver (RX) with baud-rate clock and data recovery (CDR), which is essential for high-throughput low-latency communication in high-performance computing systems. The proposed low-power global clock distribution not only significantly reduces power consumption across multi-lane RXs but is capable of compensating for the frequency offset without any phase interpolators (PIs). To this end, a fractional divider (FDIV) controlled by CDR is placed close to the global phase locked loop. Moreover, in order to address the suboptimal lock point of conventional baud-rate phase detectors, the proposed CDR employs a background eye-climbing algorithm (ECA), which optimizes the sampling phase and maximizes the vertical eye margin (VEM). Fabricated in a 28 nm CMOS process, the proposed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times 32$ </tex-math></inline-formula> Gb/s RX shows a low integrated fractional spur of −40.4 dBc at a 2500 ppm frequency offset. Furthermore, it improves bit-error-rate (BER) performance by increasing the VEM by 26 mV. The entire RX achieves the energy efficiency of 1.8 pJ/bit with the aggregate data rate of 128 Gb/s.

This article presents a ring oscillator (RO)-based all-digital phase-locked loop (ADPLL) that is implemented with a high-gain analog closed loop for supply noise compensation (ACSC). The ACSC not only allows high-frequency oscillation of the RO but also is robust over process, voltage, and temperature (PVT) variations thanks to its replica-based configuration. Moreover, a comprehensive analysis of the noise contribution of the ACSC is conducted for the ADPLL to retain its low-jitter output. Implemented in 40-nm CMOS technology, the ADPLL, with a 1.1-V supply, achieves an rms jitter of 289 fs at 8 GHz without any injected supply noise. Under a 20- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}{\text{V}}_{\text{rms}}$ </tex-math></inline-formula> white supply noise, the ADPLL gives rms jitters of 8.7 and 0.63 ps at 8 GHz when the ACSC is disabled and enabled, respectively. The overall power consumption and the area of the presented ADPLL are 9.48 mW and 0.055 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{mm}{}^2$ </tex-math></inline-formula> , respectively.

ABSTRACT As four‐level pulse‐amplitude‐modulation (PAM‐4) signal becomes widely adopted for high‐speed wireline communication, robust equalization is crucial due to reduced eye‐opening and increased sensitivity to channel loss, compared to PAM‐2. Utilizing analog‐to‐digital converters and digital signal processing with a feed‐forward equalizer (FFE) and a decision‐feedback equalizer (DFE), conventional equalizer adaptation may result in suboptimal bit‐error‐rate (BER) performance. This letter introduces an improved training algorithm to obtain the optimal equalizer configuration (i.e., main tap position in FFE and the DFE tap coefficient). The experimental results demonstrate superior BER performance of the proposed algorithm compared to the conventional approaches.

This study focuses on the manoeuvring characteristics of model- and full-scale ships. Various methods, including free-running model tests (FRMTs), computational fluid dynamics (CFD), and theoretical approaches, were employed to estimate ship manoeuvring performance. However, these methods are typically simulated at model-scale, which introduces discrepancies in the Reynolds number due to Froude scaling laws. Although numerous studies have investigated scale effects, most have concentrated on ship resistance, with limited research on manoeuvring performance. To address this gap, this study developed a free-running CFD simulation model for both a model-scale and full-scale ONRT. The study involved a detailed analysis of manoeuvring trajectories, forces, and moments. This analysis aimed to highlight differences in manoeuvring performance caused by Reynolds number discrepancies between model- and full-scale ships, providing a quantitative assessment of performance variations across scales and contributing to a more accurate understanding of manoeuvring characteristics at full scale.

This paper presents an energy-efficient ADC-based PAM4 receiver fabricated in a 28 nm CMOS process. The proposed design features a four-way time-interleaved charge-based subranging ADC that integrates three key techniques: 1) a wide input-tolerant charge-based comparator that extends the limited input range and improves operational robustness of conventional low-power charge-based comparators, 2) a conditional-branching-based partial activation scheme that improves the area and capacitive efficiency of the subranging architecture, and 3) a time-based calibration technique that addresses potential performance degradation in the conditional branching scheme. These design techniques enable robust and power-efficient ADC operation optimized for high-speed applications while minimizing the interleaving factor. The prototype ADC achieves an SNDR of 29.1 dB (ENOB = 4.54 bits) at 4 GHz input and 8 GS/s. Operating at 20 Gb/s under a 33.1 dB insertion loss channel, the proposed receiver effectively compensates for ISI, achieving a pre-FEC BER of 1.8E-8 with a competitive energy efficiency of 3.09 pJ/b. These results demonstrate that the proposed low-interleaving architecture provides a scalable and power-efficient solution for high-speed wireline communication.

This paper presents an I/O interface with Xtalk Minimizing Affine Signaling (XMAS), which is designed to support high-speed data transmission in high-density interconnects susceptible to crosstalk. The operating principles of XMAS are elucidated through rigorous analyses, and its advantages over existing signaling are validated through numerical experiments. XMAS not only demonstrates exceptional crosstalk removing capabilities but also exhibits robustness against noise, especially simultaneous switching noise. Fabricated in a 28-nm CMOS process, the prototype XMAS transceiver achieves a wire density of 3.6TB/s/mm and an energy efficiency of 0.65pJ/b. Compared to the single-ended signaling, the crosstalk-induced peak-to-peak jitter of the received eye with XMAS is reduced by 75% at 10GS/s/pin data rate, and the horizontal eye opening extends to 0.2UI at a bit error rate <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$<10{}^{-12}$</tex-math> </inline-formula>.

The chip industry is undergoing a market transition from mass production to mass customization. Rapid market changes require agile responses and diversified product designs, particularly in interface circuits managing chip-to-chip communication. To facilitate these shifts, this paper proposes a machine learning-based method for rapidly and accurately predicting and analyzing the performance of high-speed transceivers, along with an evaluation methodology utilizing the proposed approach. Especially, using the process technology information as input in the dataset, this is the first work to predict the performance of a design across different technologies, which will be invaluable in architecting and optimizing designs during the early stages of development. By simulating each functional block, we gather a dataset for parameterized design and performance and incorporate device characteristics from lookup tables. The transmitter, which operates like digital circuits, is trained using parameterized signals with a DNN, while the receiver, containing analog blocks and feedback structures, employs hybrid LSTM-DNN learning with time-series input and output. Our model, trained with a 40 nm design, demonstrates high accuracy in predicting performance even with different foundries and technologies. The majority of performance parameters show an R<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> value exceeding 0.9, indicating strong predictive accuracy under varying conditions. This method provides valuable insights for early-stage design optimization and process technology scaling, offering potential for broader applications in circuit design areas.

Die-to-die interfaces in high-performance computing systems demand high data transmission bandwidth, low latency, and low power consumption [1], [3]–[6]. Conventionally, current-mode, matched clocking architectures are used in high-speed transceivers for their superior jitter characteristics. However, these architectures face challenges, including latency limitations due to bias settling time and the high power consumption of current-mode circuits. To address challenges, we propose a digital-intensive, unmatched clocking architecture with background tracking schemes that compensate for power supply-induced jitter (PSIJ) at the receiver (RX) [7] and the reference mismatch between the transmitter (TX) and RX of single-ended (SE) transceiver structures [4].