A 0.38-mW 200-kHz-BW Digital-Intensive Single-Opamp Fourth-Order Continuous-Time Delta-Sigma Modulator With Third-Order Digital Noise Coupling in 28-nm CMOS
Kent Edrian Lozada, Ye-Dam Kim, Ho-Jin Kim, Youngjae Cho, Michael Choi, Seung-Tak Ryu
IEEE, JSSC, 2024
2
12-bit High-Voltage Current-Steering-Assisted R-2R DAC with RCM and Parallel Switch for Satellite-Applications
Charlie Tahar, Changyeop Lee, Hyojun Kim, Seung-Tak Ryu
IEEE TNS, 2024
3
An M-Metric Readout Circuit for MLC Phase-Change Memory With a Comparator-Based Push-Pull Bit-Line Driver
Ji-Wook Kwon, Dong-Hwan Jin, Min-Jae Seo, Seung-Tak Ryu
IEEE TCAS-II, 2024
4
DR Loss-Free Dithering-Based Digital Background Linearity Calibration for SAR-Assisted Multi-Stage ADCs with Digital Input-Interference Cancellation
Lizhen Zhang, Bo Gao, Kun-Woo Park, Kent Edrian Lozada, Raymond Mabilangan, Hyeongjin Kim, Jianhui Wu, Seung-Tak Ryu
IEEE, OJCAS, 2024
5
SAR-Assisted Energy-Efficient Hybrid ADCs
Kent Edrian Lozada, Dong-Jin Chang, Dong-Ryeol Oh, Min-Jae Seo, Seung-Tak Ryu
IEEE, OJ-SSCS, 2024
6
A 25-kHz-BW 97.4-dB-SNDR SAR-Assisted Continuous-Time 1-0 MASH Delta-Sigma Modulator With Digital Noise Coupling
Dong-Hun Lee*, Kent Edrian Lozada*, Ye-Dam Kim, Ho-Jin Kim, Youngjae Cho, Michael Choi, Seung-Tak Ryu
IEEE, JSSC, 2024
7
A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC
Jae-Hyun Chung, Ye-Dam Kim, Chang-Un Park, Kun-Woo Park, Min-Jae Seo, Dong-Ryeol Oh, Seung-Tak Ryu
IEEE, JSSC, 2024
8
A 4th-Order Continuous-Time Delta-Sigma Modulator with Hybrid Noise-Coupling
Kent Edrian Lozada, Il-Hoon Jang, Gyeom-Je Bae, Dong-Hun Lee, Ye-Dam Kim, Hankyu Lee, Seong Joong Kim, Seung-Tak Ryu
IEEE, TCAS-II, 2022
9
A 7-bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique
Dong-Ryeol Oh, Min-Jae Seo, Seung-Tak Ryu
IEEE, JSSC, 2022
10
MixedNet: Network Design Strategies For Cost-Effective Quantized CNNs